A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 35

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
CLKA/B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard TTL,
LVTTL, 3.3 V PCI, or 5 V PCI specifications. The clock input
is buffered prior to clocking the R-cells. If unused, these
pins must be fixed LOW or HIGH on the board. They must
not be left floating (for HiRel A54SX72A, these clocks can
be configured as user I/O).
QCLKA/B/C/D, I/O
These four pins are the clock inputs for the quadrant
clock distribution networks and only exist on HiRel
A54SX72A. Input levels are compatible with standard
TTL, LVTTL, 3.3 V PCI, or 5 V PCI specifications. Each of
these clock inputs can drive up to a quarter of the chip,
or they can be grouped together to drive multiple
quadrants. The clock input is buffered prior to clocking
the R-cells. If not used as a clock, each input will behave
as a regular I/O.
GND
LOW supply voltage.
HCLK
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL, LVTTL, 3.3 V PCI,
or 5 V PCI specifications. This input is wired directly to
each R-cell and offers clock speeds independent of the
number of R-cells being driven. If not used, this pin must
set LOW or HIGH on the board. It must not be left
floating.
1. 70
Ω
series termination should be placed on the board to enable probing capability.
Clock A/B
Quadrant Clock A/B/C/D, I/O
Ground
Dedicated (hardwired) Array Clock
v2.0
I/O
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard
TTL, LVTTL, 3.3 V PCI, or 5 V PCI specifications. Unused I/O
pins are automatically tristated by the Designer
software.
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or left floating
with no effect on the operation of the device.
PRA/B, I/O
The Probe pin is used to put out data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
Probe pin to allow real-time diagnostic output of any
signal path within the device. A Probe pin can be used as
a user-defined I/O when verification has been completed.
The pin’s probe capabilities can be disabled permanently
to protect programmed design confidentiality.
TCK, I/O
Test clock input for diagnostic probe and device
programming. In Flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to
page
boundary scan state machine reaches the "logic reset"
state.
1-7). This pin functions as an I/O when the
1
1
Input/Output
No Connection
Probe A/B
Test Clock
HiRel SX-A Family FPGAs
Table 1-5 on
1-31