A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 151

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 1 (cont’d)
Packaging v1.1
Revision 0 (Jan 2008) This document was previously in datasheet v2.1. As a result of moving to the
v2.1
(July 2007)
v2.0
(April 2007)
The
The
The
The
handbook format, Actel has restarted the version numbers. The new version
number is 51700098-001-0.
CoreMP7 information was removed from the "Features and Benefits" section.
The M1 device part numbers have been updated in Table 4 • ProASIC3E
Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed
Grade and Temperature Grade Matrix", and "Speed Grade and Temperature
Grade Matrix".
The words "ambient temperature" were added to the temperature range in the
"Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix",
and "Speed Grade and Temperature Grade Matrix" sections.
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
The caption "Main (chip)" in Figure 2-9 • Overview of Automotive ProASIC3
VersaNet Global Network was changed to "Chip (main)."
The T
changed to T
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
In the "Temperature Grade Offerings" section, Ambient was deleted.
Ambient was deleted from "Temperature Grade Offerings".
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
The "PLL Macro" section was updated to include power-up information.
Table 2-13 • ProASIC3E CCC/PLL Specification was updated.
Figure 2-19 • Peak-to-Peak Jitter Definition is new.
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
The "RESET" section was updated with read and write information.
The "RESET" section was updated with read and write information.
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
"208-Pin PQFP"
"324-Pin FBGA"
"484-Pin FBGA"
"896-Pin FBGA"
J
parameter in Table 3-2 • Recommended Operating Conditions was
A
, ambient temperature, and table notes 4–6 were added.
pin table for A3PE3000 was updated.
pin table for A3PE3000 is new.
pin table for A3PE3000 is new.
pin table for A3PE3000 is new.
R e v i s i o n 9
Changes
ProASIC3E Flash Family FPGAs
iii, iv, iv
Page
2-15
2-30
2-18
2-25
2-25
3-13
3-27
3-41
iv, iv
2-15
2-21
2-28
2-34
2-64
2-40
N/A
ii, iii,
3-6
2-9
3-2
iii
iii
iv
i
i
4 -3