A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 83

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Conditioning Circuits
Table 2-98 • ProASIC3E CCC/PLL Specification
Note:
Figure 2-38 • Peak-to-Peak Jitter Definition
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Serial Clock (SCLK) for Dynamic PLL
Number of Programmable Values in Each
Programmable Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
2. This delay is a function of voltage and temperature. See
3. T
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
temperature and voltage supply levels, refer to
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
J
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
= 25°C, VCC = 1.5 V.
Peak-to-peak jitter measurements are defined by T
Output Signal
CCC Electrical Specifications
Timing Characteristics
4
1, 2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
1
CCC_OUT
IN_CCC
2, 3
2, 3
OUT_CCC
Table 2-6 on page 2-5
2, 3
T
period_max
peak-to-peak
Table 2-6 on page 2-5
R e v i s i o n 9
Network Used
Minimum
1 Global
0.50%
1.00%
1.75%
2.50%
0.025
0.75
48.5
1.5
0.6
= T
for derating values.
period_max
T
Max Peak-to-Peak Period Jitter
period_min
for deratings.
Typical
160
2.2
– T
period_min
ProASIC3E Flash Family FPGAs
Networks Used
Maximum
3 Global
.
0.70%
1.20%
2.00%
5.60%
51.5
5.56
5.56
350
350
125
300
1.5
6.0
1.6
0.8
32
Units
MHz
MHz
MHz
ms
ps
ns
µs
ns
ns
ns
ns
ns
%
2- 71