A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 79

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-36 • Timing Model and Waveforms
Table 2-94 • Register Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
CLK
Data
EN
PRE
Out
CLR
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
Description
J
50%
t
= 70°C, Worst-Case VCC = 1.425 V
WPRE
50%
50%
50%
t
t
RECPRE
WCLR
R e v i s i o n 9
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-6 on page 2-5
50%
t
CKMPWH
ProASIC3E Flash Family FPGAs
t
50%
0.55 0.63 0.74
0.43 0.49 0.57
0.00 0.00 0.00
0.45 0.52 0.61
0.00 0.00 0.00
0.40 0.45 0.53
0.40 0.45 0.53
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.32 0.37 0.43
0.36 0.41 0.48
REMPRE
–2
t
CKMPWL
50%
for derating values.
–1
Std. Units
50%
50%
t
REMCLR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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