A3PE1500-FGG676 Actel, A3PE1500-FGG676 Datasheet - Page 154

• Manufacturer Part Number: A3PE1500-FGG676
• Description: FPGA - Field Programmable Gate Array 1500K System Gates
• Manufacturer: Actel

Specifications of A3PE1500-FGG676

• Processor Series: A3PE1500
• Core: IP Core
• Maximum Operating Frequency: 231 MHz
• Number Of Programmable I/os: 444
• Data Ram Size: 276480
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1.5 M
• Package / Case: FPBGA-676
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 6
Revision
Advance v0.5
(continued)
Advance v0.4
(October 2005)
Advance v0.3
Figure 2-11 was updated.
The CCC Output Peak-to-Peak Period Jitter F
2-13 • ProASIC3E CCC/PLL Specification.
EXTFB was removed from Figure 2-27 • CCC/PLL Macro.
The LVPECL specification in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3E Devices was updated.
Table 2-15 • Levels of Hot-Swap Support was updated.
The "Cold-Sparing Support" section was updated.
"Electrostatic Discharge (ESD) Protection" section was updated.
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
The "VJTAG JTAG Supply Voltage" pin description was updated.
The "V
include information on what happens when the pin is tied to ground.
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
The "Programming" section was updated to include information concerning
serialization.
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
The "DC and Switching Characteristics" chapter was updated with new
information.
Table 3-6 was updated.
In Table 3-10, PAC4 was updated.
Table 3-19 was updated.
The note in Table 3-24 was updated.
All Timing Characteristics tables were updated from LVTTL to Register Delays
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
F
The "Packaging Tables" table was updated.
The "Clock Resources (VersaNets)" section was updated.
The "VersaNet Global Networks and Spine Access" section was updated.
The "PLL Macro" section was updated.
Figure 2-27 was updated.
Figure 2-20 was updated.
TCKMAX
PUMP
was updated in Table 3-98.
Programming Supply Voltage" pin description was updated to
R e vi s i o n 9
Changes
CCC_OUT
was updated in Table
on page
Starting
3-26 to
3-74 to
Page
2-28
2-50
3-20
3-23
2-30
2-64
2-34
2-34
2-35
2-50
2-50
2-50
2-51
2-53
2-54
3-64
3-79
3-80
2-15
2-28
2-19
3-8
3-1
3-5
2-9
2-9
2-9
ii