ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 229

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.2.5
• I20ST (bit 0)
• I20SP (bit 1)
• I20RS (bit 2)
• I20ACT (bit 7)
Address: 0F2A3H
Access: R/W
Access size: 8 bits
Initial value: 00H
I2C0CON is a special function register (SFR) to control transmit and receive operations.
[Description of Bits]
Note:
In the case of a multi-master, check that the I
communication.
Initial value
I2C0CON
The I20ST bit is used to control the communication operation of the I
“1”, communication starts. When “1” is overwritten to the I20ST bit in a control register setting wait state after
transmission/reception of acknowledgment, communication starts again.
communication is stopped forcibly.
The I20SP bit is a write-only bit used to request a stop condition. When the I20SP bit is set to “1”, the I
shifts to the stop condition and communication stops. When the I20SP bit is read, “0” is always read.
The I20RS bit is a write-only bit used to request a repeated start. When this bit is set to “1” during data
communication, the I
I20RS can be set to “1” only while communication is active (I20ST =“1”). When the I20RS bit is read, “0” is
always read.
The I20ACT bit is used to set the acknowledge signal to be output at completion of reception.
The I20ST bit can be set to “1” only when the I2C bus interface is in an operation enable state (I20EN = “1”).
When the I20SP bit is set to “1”, the I20ST bit is set to “0”.
R/W
I20ACT
I20RS
I20ST
I20SP
0
1
0
1
0
1
0
1
I
2
C Bus 0 Control Register (I2C0CON)
I20ACT
R/W
Stops communication (initial value)
Starts communication
No stop condition request (initial value)
Stop condition request
No repeated start request (initial value)
Repeated start request
Acknowledgment data “0” (initial value)
Acknowledgment data “1”
7
0
2
C bus shifts to the repeated start condition and communication restarts from the slave address.
R/W
—
6
0
R/W
—
5
0
2
C bus is in a free state by using the I20BB flag of I2C0STAT and start
Description
Description
Description
Description
R/W
—
16 – 6
4
0
R/W
—
0
3
2
C bus interface. When the I20ST bit is set to
ML610Q431/ML610Q432 User’s Manual
I20RS
W
2
0
When the I20ST bit is set to “0”,
Chapter 16 I
I20SP
W
1
0
2
C Bus Interface
I20ST
R/W
0
0
2
C bus