ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 401

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ML610Q432A-NNNTC03A7

Manufacturer Part Number
ML610Q432A-NNNTC03A7
Description
MCU 8BIT 64K FLASH 128-TQFP
Manufacturer
Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

Core Processor
nX-U8/100
Core Size
8-Bit
Speed
4.2MHz
Connectivity
I²C, SSP, UART/USART
Peripherals
LCD, Melody Driver, POR, PWM, WDT
Number Of I /o
14
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 2x12b, 2x24b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
ML610Q432A-NNNTC03A7
Manufacturer:
Rohm
Quantity:
750
Part Number:
ML610Q432A-NNNTC03A7
Manufacturer:
Rohm Semiconductor
Quantity:
10 000
28.3.2
Activation (ON) and deactivation (OFF) of the Battery Level Detector are controlled by setting the ENBL bit of the
Battery Level Detector control register (BLDCON1), and the result of the comparison of the power supply voltage
(VDD) to the threshold voltage is output to the BLDF bit of BLDCON1.
When ENBL, the enable control bit of the Battery Level Detector, is set to “1”, the detector is activated (ON). When
ENBL is set to “0”, the detector is deactivated (OFF) and has no supply current.
BLDF indicates the result of comparison. When BLDF bit is set to “1”, it indicates the power supply voltage is lower
than the threshold voltage. When BLDF bit is set to “0”, it indicates the power supply voltage (VDD) is higher than the
threshold voltage. The Battery Level Detector requires a settling time. Read BLDF bit 1ms or more after ENBL bit is
set to “1”.
Figure 28-2 shows an example of the operation timing diagram.
The operations in Figure 28-2 are described below.
Note:
Select the threshold voltage (VCMP) when the ENBL bit is “0”.
Threshold voltage
1 The Battery Level Detector is activated (ON) by setting the ENBL bit to “1”.
2 Wait the settling time (min. 1 ms) of the Battery Level Detector.
3 Read BLDF bit.
4 Set ENBL bit to “0”.
Operation
Operation of Battery Level Detector
ENBL
BLDF
V
CMP
V
SS
Figure 28-2 Example of Operation Timing Diagram
Set ENBL
1
Wait for settling time of BLD
(Min. 1 ms)
“1” or “0”
V
CMP
2
28 – 6
Read BLDF
3
ML610Q431/ML610Q432 User’s Manual
4
Set ENBL
Chapter 28 Battery Level Detector

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