ML610Q432A-NNNTC03A7 Rohm Semiconductor, ML610Q432A-NNNTC03A7 Datasheet - Page 387

• Manufacturer Part Number: ML610Q432A-NNNTC03A7
• Description: MCU 8BIT 64K FLASH 128-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q432A-NNNTC03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 4.2MHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, Melody Driver, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.3 Description of Operation
27.3.1
Figure 27-6 shows the operation of the LCD drivers and the bias generation circuit.
1 System reset causes the bias generation circuit and the LCD drivers to stop operation and Vss level to be output to
2 By using the bias circuit control register (BIASCON), select 1/3 bias or 1/4 bias and lock of bias voltage multiplying,
3 When the programmable display allocation function is used, set LCD allocation data in the display allocation
4 Set a frame frequency and a duty by using the display mode register 0 (DSPMOD0). When using the programmable
5 Set display data in the display registers (DSPR00 to DSPRFE).
6 After elapse of the bias activation time (T
each of the common and segment pins.
and set the bias generation circuit to on (BSON = “1”).
registers A and B (DS0C0A to DS63C7A and DS0C0B to DS63C7B).
display allocation function, set the DASN bit of DSPMOD1 register to “1” and set DADM1 bit to “1” to select type 3
for the display register segment map. When not using the programmable display allocation function, set the DASN bit
to “0” and select a type of segment map for display registers.
LMD0 bits of the display control register (DSPCON). (Display waveform is output to each segment pin.)
For the bias activation time (T
Operation of LCD Drivers and Bias Generation Circuit
COM0 to COM15/23
BIASCON.BSON
LCD bias voltage
SEG0 to SEG63
Common output
Segment output
Figure 27-6 Operation of LCD Drivers and Bias Generation Circuit
LMD1, LMD0
RESET_N
V
L1
Reset
to V
L4
BIAS
), see the “Electrical Characteristics” Section in Appendix C.
1
BIAS
V
V
SS
SS
) or longer, set the mode to display mode by using the LMD1 and
2
BIAS activation time (T
27 – 35
345
Generation of LCD bias voltage
BIAS
6
ML610Q431/ML610Q432 User’s Manual
)
Common output waveform
Segment output waveform
Chapter 27 LCD Drivers