D2-24044-MR-T Intersil, D2-24044-MR-T Datasheet - Page 14

• Manufacturer Part Number: D2-24044-MR-T
• Description: IC DGTL AMP AUDIO PWR D 38HTSSOP
• Manufacturer: Intersil
• Series: D2Audio™r
• Type: Class Dr

Specifications of D2-24044-MR-T

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Max Output Power X Channels @ Load: 30W x 2 @ 8 Ohm
• Voltage - Supply: 9 V ~ 26 V
• Mounting Type: Surface Mount
• Package / Case: 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Output Mode Configurations
The D2-24044 device supports four amplifier output
configuration modes, utilizing the device’s 4 power stage
outputs.
Configuration selection is controlled by the OCFG0 and
OCFG1 pins, by connecting them to either a high
(+3.3V, PWMVDD = 1) or low (ground = 0) level.
Settings are chosen based on the output configuration
and topology of the design. Their connection is to be
hard-connected on the design, and they are not
intended to be dynamic or subject to change during
system operation.
OCFG1 OCFG0
CONFIG PINS
0
0
1
1
0
1
0
1
CONFIG
TABLE 1. D2-24044 CONFIGURATION PWM AND OUTPUT CHANNEL ASSIGNMENTS
“00”
“01”
“10”
“11”
2-Quadrant PWM Drive
14
CONFIGURATION
DESCRIPTION
(Ref. Figure 11)
(Ref. Figure 12)
(Ref. Figure 13)
(Ref. Figure 14)
Full Bridge,
Half-Bridge
Half-Bridge
PWM Drive
Full Bridge
Full Bridge
2-Channel
2-Channel
2-Channel
1-Channel
4-Channel
3-Level
plus
High-Side FET PWM Input Assignments
High-Side FET PWM Input Assignments
Output
High-Side FET PWM Input Assignments
Output
High-Side FET PWM Input Assignments
OUTA
PWM1
Low-Side FET PWM Input Assignments
PWM2
PWM1
Low-Side FET PWM Input Assignments
PWM2
PWM1
Low-Side FET PWM Input Assignments
PWM2
PWM1
Low-Side FET PWM Input Assignments
PWM2
Ch. 1
Ch. 1
Channel 1
Channel 1
Output
Output
POWER STAGE OUTPUT
D2-24044
Output
Output
OUTB
PWM3
PWM4
PWM2
PWM1
PWM3
PWM4
PWM3
PWM4
Ch 2
Ch 2
For each of the four configurations, the PWM input pin
signals route to the individual FETs of each of the power
stages to implement the channel drive and topology
needed for those configurations. Figures 11, 12, 13, and
14 show this routing of the PWM inputs to each of the
power stages, and how the particular topology is
implemented for that configuration. Table 1 shows the
configuration functions that are defined with the
combinations of the OCFG pins, and these diagrams
show the implementation that is listed in this table.
Output
OUTC
PWM5
PWM6
PWM3
PWM4
PWM5
PWM6
PWM5
PWM6
Ch. 3
Channel 2
Channel 2
Channel 3
Output
Output
Output
Output
OUTD
PWM7
PWM8
PWM4
PWM3
PWM6
PWM5
PWM7
PWM8
Ch 4
nERRORA nERRORB nERRORC nERRORD
nERRORA & nERRORB
nERRORA & nERRORB
Channel 1
Channel 1
nERRORA
nERRORA
Use for
Protect
Use for
Protect
Connect (wire-or)
Channel 1 Protect
Connect (wire-or)
Channel 1 Protect
Use for Output
Use for Output
together.
together.
nERROR CHANNEL USE
Channel 2
Channel 2
nERRORB
nERRORB
Use for
Use for
Protect
Protect
nERRORC & nERRORD
nERRORC & nERRORD
nERRORC & nERRORD
Channel 3
nERRORC
Use for
Protect
Channel 2 Protect
Channel 2 Protect
Channel 3 Protect
Connect (wire-or)
Connect (wire-or)
Connect (wire-or)
Use for Output
Use for Output
Use for Output
September 3, 2010
together.
together.
together.
nERRORD
Channel 4
Use for
Protect
FN7678.0