74LVC8T245BQ,118 NXP Semiconductors, 74LVC8T245BQ,118 Datasheet - Page 22

• Manufacturer Part Number: 74LVC8T245BQ,118
• Description: TXRX 8BIT TRANSLATING DHVQFN24
• Manufacturer: NXP Semiconductors

Specifications of 74LVC8T245BQ,118

• Logic Family: 74LVC
• Number Of Channels Per Chip: 2
• Propagation Delay Time: 5.4 ns, 8.9 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Package / Case: DHVQFN-24
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-5279-2

NXP Semiconductors
74LVC_LVCH8T245
Product data sheet
13.2 Bidirectional logic level-shifting application
13.3 Power-up considerations
Figure 15
level-shifting application.
Table 16
and then from system-2 to system-1.
Table 16.
[1]
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 17.
State DIR CTRL OE
V
0 V
1.8 V
2.5 V
3.3 V
5.0 V
1
2
3
4
Fig 15. Bidirectional logic level-shifting application
CC(A)
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
DIR CTRL
V
I/O-1
H
H
L
L
CC1
gives a sequence that will illustrate data transmission from system-1 to system-2
Schematic given for one channel.
Pull-up or pull-down only needed for 74LVC8T245.
OE
shows the 74LVC8T245; 74LVCH8T245 being used in a bidirectional logic
Description bidirectional logic level-shifting application
Typical total supply current (I
V
0 V
0
< 1
< 1
< 1
< 1
system-1
CC(B)
All information provided in this document is subject to legal disclaimers.
PULL-UP/DOWN
L
H
H
L
Rev. 2 — 11 February 2011
V
CC1
1.8 V
< 1
< 2
< 2
< 2
2
output
Z
Z
input
I/O-1
74LVC8T245; 74LVCH8T245
V
CC(A)
GND
A
I/O-2
input
Z
Z
output
8-bit dual supply translating transceiver; 3-state
2.5 V
< 1
< 2
< 2
< 2
< 2
CC(A)
74LVCH8T245
74LVC8T245
+ I
Description
system-1 data to system-2
system-2 is getting ready to send data to
system-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on bus hold.
DIR bit is set LOW. I/O-1 and I/O-2 still are
disabled. The bus-line state depends on bus
hold.
system-2 data to system-1
CC(B)
)
3.3 V
< 1
< 2
< 2
< 2
< 2
OE
B
V
DIR
CC(B)
V
PULL-UP/DOWN
CC2
[1]
5.0 V
< 1
2
< 2
< 2
< 2
system-2
© NXP B.V. 2011. All rights reserved.
Unit
A
A
A
A
A
V
I/O-2
CC2
001aak439
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