PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 20

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

Table 8:
Datasheet
20
Notes:
1.
2.
3.
4.
Mode
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[15:0].
ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into
the write buffer. This is followed by up to 512 words of data.Then the confirm command (0xD0) is
issued, triggering the array programming operation.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1=<N<=512. The
subsequent cycles load data words into the program buffer at a specified address until word count is
achieved, after the data words are loaded, the final cycle is the confirm cycle 0xD0)
Block Erase
Program/Erase Suspend
Program/Erase Resume
Lock Block
Unlock Block
Program OTP register
Program Lock Register
STS Configuration
Extended Flash Interface
Command Bus Cycles (Sheet 2 of 2)
Command
(4)
Cycles
Bus
> 2
2
1
1
2
2
2
2
2
Addr
OTP-RA
First Bus Cycle
DnA
DnA
LRA
WA
BA
BA
BA
BA
(1)
Numonyx™ StrataFlash
Data
0xB0
0xD0
0xC0
0xC0
0xB8
0xEB
0x20
0x60
0x60
(2)
Addr
OTP-RA
LRA
WA
Second Bus Cycle
BA
---
---
BA
BA
BA
(1)
Register Data
®
Sub-Op code
Embedded Memory (J3-65nm)
Data
OTP-D
0xD0
0xD0
0x01
LRD
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(2)
Addr
Last Bus Cycle
WA
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December 2008
(1)
319942-02
Data
0xD0
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(2)