PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 43

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

Numonyx™ StrataFlash
15.2
Table 23: AC Read Specification
Notes:
1.
2.
3.
4.
5.
December 2008
319942-02
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
Nbr.
CE
of CE0, CE1, or CE2 that disables the device
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
OE# may be delayed up to t
t
Sampled, not 100% tested.
For devices configured to standard word/byte read mode, R15 (t
ELQV
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
AVQV
ELQV
GLQV
PHQV
ELQX
GLQX
EHQZ
GHQZ
OH
ELFL/
FLQV/
FLQZ
EHEL
APA
GLQV
Symbol
X
low is defined as the falling edge of CE0, CE1, or CE2 that enables the device. CE
.
t
t
ELFH
FHQV
AC Read Specifications
Chip enable truth table can be found on
Test configuration can be found in
Read/Write Cycle Time
Address to Output Delay
CE
OE# to Non-Array Output Delay
RP# High to Output Delay
CE
OE# to Output in Low Z
CE
OE# High to Output in High Z
Output Hold from Address, CE
Whichever Occurs First
CE
BYTE# to Output Delay
BYTE# to Output in High Z
CEx High to CEx Low
Page Address Access Time
OE# to Array Output Delay
®
X
X
X
X
to Output Delay
to Output in Low Z
High to Output in High Z
Low to BYTE# High or Low
Embedded Memory (J3-65nm)
ELQV
Parameter
-t
GLQV
after the falling edge of CE0, CE1, or CE2 that enables the device without impact on
X
, or OE# Change,
Table 22 on page 42
Easy BGA
Easy BGA
Easy BGA
Package
TSOP
TSOP
TSOP
Table 6 on page 15
APA
) will equal R2 (t
Min
105
95
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
AVQV
Max
X
105
105
150
95
95
25
20
15
10
25
25
—
—
—
—
—
—
1
1
high is defined as the rising edge
).
Unit
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
1,2,3,4
Notes
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
4, 5
Datasheet
43