PC28F256J3F95A NUMONYX, PC28F256J3F95A Datasheet - Page 46

• Manufacturer Part Number: PC28F256J3F95A
• Description: IC FLASH 256MBIT 95NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F256J3F95A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (32M x8, 16M x16)
• Speed: 95ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 898244; 898244; PC28F256J3F95 898244

15.3
Table 24: AC Write Specification
Datasheet
46
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Nbr.
W11
W14
W13
W15
W1
W2
W3
W4
W5
W6
W7
W8
W9
t
t
t
t
t
t
t
t
t
t
t
t
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
VPWH
WHGL
WHRL
QVVL
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
A write operation can be initiated and terminated with either CE
Sampled, not 100% tested.
Write pulse width (t
(whichever goes high first). Hence, t
Write pulse width high (t
low (whichever goes low first). Hence, t
For array access, t
STS timings are based on STS configured in its RY/BY# default mode.
V
= 0).
t
PEN
PHWL
Symbol
(t
should be held at V
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
EHRL
AVEH
EHAX
EHGL
DVEH
VPEH
EHWH
EHDX
PHEL
AC Write Specification
CE
high is defined at the rising edge of CE0, CE1, or CE2 that disables the device. Chip
enable truth table can be found in
)
)
)
)
)
)
)
)
X
)
)
low is defined as the falling edge of CE0, CE1, or CE2 that enables the device. CE
RP# High Recovery to WE# (CE
CE
Write Pulse Width
Data Setup to WE# (CE
Address Setup to WE# (CE
CE
Data Hold from WE# (CE
Address Hold from WE# (CE
Write Pulse Width High
V
Write Recovery before Read
WE# (CE
V
PEN
PEN
AVQV
X
X
WP
(WE#) Low to WE# (CE
(WE#) Hold from WE# (CE
Setup to WE# (CE
Hold from Valid SRD, STS Going High
) is defined from CE
is required in addition to t
PENH
WPH
X
) High to STS Going Low
) is defined from CE
until determination of block erase, program, or lock-bit configuration success (SR[5:3,1]
WP
Parameter
= t
WPH
X
X
) Going High
) Going High
X
X
WLWH
) High
X
or WE# going low (whichever goes low last) to CE
= t
) Going High
X
X
) Going Low
) High
WHWL
X
X
X
= t
) High
WHGL
) Going Low
or WE# going high (whichever goes high first) to CE
ELEH
= t
Table 6 on page 15
for any accesses after a write.
EHEL
= t
Numonyx™ StrataFlash
WLEH
= t
X
WHEL
= t
or WE#.
ELWH
= t
EHWL
.
.
Min
150
50
20
50
50
—
0
0
0
0
0
0
0
®
Embedded Memory (J3-65nm)
Max
500
—
—
—
—
—
—
—
—
—
—
—
—
X
or WE# going high
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X
or WE# going
December 2008
1,2,3,7,8
319942-02
Notes
1,2,3
1,2,4
1,2,4
1,2,5
1,2,3
1,2,6
1,2,7
1,2,
1,2,
1,2,
1,2
1,2
X