SC28L92A1A NXP Semiconductors, SC28L92A1A Datasheet - Page 2

• Manufacturer Part Number: SC28L92A1A
• Description: UART, DUAL, 3.3V OR 5V, SMD, 28L92
• Manufacturer: NXP Semiconductors

Specifications of SC28L92A1A

• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 3.63V, 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Data Rate: 230.4Kilobaud
• Uart Features: Programmable Channel Mode, Line Break Detection & Generation
• Rohs Compliant: Yes

NXP Semiconductors
2. Features
SC28L92_7
Product data sheet
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Member of IMPACT family: 3.3 V to 5.0 V, 40 C to +85 C and 68xxx or 80xxx bus
interface for all devices
Dual full-duplex independent asynchronous receiver/transmitters
16 character FIFOs for each receiver and transmitter
Pin programming selects 68xxx or 80xxx bus interface
Programmable data format
16-bit programmable counter/timer
Programmable baud rate for each receiver and transmitter selectable from:
Parity, framing, and overrun error detection
False start bit detection
Line break detection and generation
Programmable channel mode
Multi-function 7-bit input port (includes IACKN)
Multi-function 8-bit output port
Versatile interrupt system
Maximum data transfer rates: 1 - 1 Mbit/s, 16 - 1 Mbit/s
Automatic wake-up mode for multi-drop applications
Start-end break interrupt/status
Detects break which originates in the middle of a character
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5 data to 8 data bits plus parity
Odd, even, no parity or force parity
1 stop, 1.5 stop or 2 stop bits programmable in
28 fixed rates: 50 kBd to 230.4 kBd
Other baud rates to 1 MHz at 16
Programmable user-defined rates derived from a programmable counter/timer
External 1 or 16 clock
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multi-drop mode (also called wake-up or 9-bit)
Can serve as clock or control inputs
Change of state detection on four inputs
Inputs have typically > 100 k pull-up resistors
Change of state detectors for modem control
Individual bit set/reset capability
Outputs can be programmed to be status/interrupt signals
FIFO status for DMA interface
Single interrupt output with eight maskable interrupting conditions
Output port can be configured to provide a total of up to six separate interrupt
outputs that may be wire ORed
Each FIFO can be programmed for four different interrupt levels
Watchdog timer for each receiver
Rev. 07 — 19 December 2007
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
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16
-bit increments
SC28L92
© NXP B.V. 2007. All rights reserved.
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