DSPIC30F5011-30I/PTG Microchip Technology, DSPIC30F5011-30I/PTG Datasheet - Page 131

• Manufacturer Part Number: DSPIC30F5011-30I/PTG
• Description: 16BIT MCU-DSP 30MHZ, SMD, 30F5011
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-30I/PTG

• Core Frequency: 30MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the conver-
sion trigger. The SSRC bits provide for up to 4 alternate
sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules or
external interrupts.
19.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing until the next sampling trigger. The ADCBUF will not
be updated with the partially completed A/D conversion
sample. That is, the ADCBUF will continue to contain
the value of the last completed conversion (or the last
value written to the ADCBUF register).
If the clearing of the ADON bit coincides with an auto-
start, the clearing has a higher priority and a new
conversion will not start.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
19.6
The A/D conversion requires 15 T
A/D conversion clock is software selected, using a
six-bit counter. There are 64 possible options for T
EQUATION 19-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 667 nsec (for V
Specifications section for minimum T
operating conditions.
 2004 Microchip Technology Inc.
AD
) must be selected to ensure a minimum T
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the A/D Conversion
Clock
T
AD
= T
CY
DD
* (0.5*(ADCS<5:0> + 1))
A/D CONVERSION CLOCK
= 5V). Refer to the Electrical
AD
. The source of the
AD
under other
AD
AD
wait is
AD
time
Preliminary
.
Example 19-1 shows a sample calculation for the
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 19-1:
dsPIC30F5011/5013
Therefore,
Set ADCS<5:0> = 40
ADCS<5:0> = 2
Minimum T
Actual T
AD
T
AD
CY
= 2 •
= 39.4
=
=
= 677 nsec
A/D CONVERSION CLOCK
CALCULATION
= 667 nsec
= 33 nsec (30 MIPS)
T
33 nsec
T
T
CY
2
AD
CY
667 nsec
2
33 nsec
(ADCS<5:0> + 1)
– 1
(40 + 1)
DS70116C-page 129
– 1