DSPIC30F5011-30I/PTG Microchip Technology, DSPIC30F5011-30I/PTG Datasheet - Page 211

• Manufacturer Part Number: DSPIC30F5011-30I/PTG
• Description: 16BIT MCU-DSP 30MHZ, SMD, 30F5011
• Manufacturer: Microchip Technology
• Series: DsPIC30Fr

Specifications of DSPIC30F5011-30I/PTG

• Core Frequency: 30MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Operating Temperature Range: -40°C To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INDEX
Numerics
12-bit Analog-to-Digital Converter (A/D) Module .............. 127
A
A/D .................................................................................... 127
AC Characteristics ............................................................ 178
AC Temperature and Voltage Specifications .................... 178
AC-Link Mode Operation .................................................. 124
Address Generator Units .................................................... 33
Alternate Vector Table ........................................................ 43
Analog-to-Digital Converter. See A/D.
Assembler
Automatic Clock Stretch...................................................... 92
B
Bandgap Start-up Time
Barrel Shifter ....................................................................... 19
Bit-Reversed Addressing .................................................... 36
Block Diagrams
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Aborting a Conversion .............................................. 129
ADCHS Register ....................................................... 127
ADCON1 Register..................................................... 127
ADCON2 Register..................................................... 127
ADCON3 Register..................................................... 127
ADCSSL Register ..................................................... 127
ADPCFG Register..................................................... 127
Configuring Analog Port Pins.............................. 58, 132
Connection Considerations....................................... 132
Conversion Operation ............................................... 128
Effects of a Reset...................................................... 131
Operation During CPU Idle Mode ............................. 131
Operation During CPU Sleep Mode.......................... 131
Output Formats ......................................................... 131
Power-down Modes .................................................. 131
Programming the Sample Trigger............................. 129
Register Map............................................................. 133
Result Buffer ............................................................. 128
Sampling Requirements............................................ 130
Selecting the Conversion Clock ................................ 129
Selecting the Conversion Sequence......................... 128
T
Load Conditions ........................................................ 178
16-bit Mode ............................................................... 124
20-bit Mode ............................................................... 124
MPASM Assembler................................................... 159
During 10-bit Addressing (STREN = 1)....................... 92
During 7-bit Addressing (STREN = 1)......................... 92
Receive Mode ............................................................. 92
Transmit Mode ............................................................ 92
Requirements............................................................ 183
Timing Characteristics .............................................. 183
Example ...................................................................... 36
Implementation ........................................................... 36
Modifier Values Table ................................................. 37
Sequence Table (16-Entry)......................................... 37
12-bit A/D Functional ................................................ 127
16-bit Timer1 Module .................................................. 63
16-bit Timer2............................................................... 69
16-bit Timer3............................................................... 69
16-bit Timer4............................................................... 74
16-bit Timer5............................................................... 74
32-bit Timer2/3............................................................ 68
32-bit Timer4/5............................................................ 73
AD
vs. Device Operating Frequencies..................... 129
Preliminary
BOR Characteristics ......................................................... 177
BOR. See Brown-out Reset.
Brown-out Reset
C
C Compilers
CAN Module ..................................................................... 105
CLKOUT and I/O Timing
Code Examples
Code Protection ................................................................ 135
Control Registers ................................................................ 46
Core Architecture
CPU Architecture Overview ................................................ 11
D
Data Accumulators and Adder/Subtractor .......................... 17
dsPIC30F5011/5013
CAN Buffers and Protocol Engine ............................ 106
DCI Module............................................................... 118
Dedicated Port Structure ............................................ 57
DSP Engine ................................................................ 16
dsPIC30F5011.............................................................. 6
dsPIC30F5013.............................................................. 7
External Power-on Reset Circuit .............................. 143
I
Input Capture Mode.................................................... 77
Oscillator System...................................................... 137
Output Compare Mode ............................................... 81
Reset System ........................................................... 141
Shared Port Structure................................................. 58
SPI.............................................................................. 86
SPI Master/Slave Connection..................................... 86
UART Receiver........................................................... 98
UART Transmitter....................................................... 97
Characteristics.......................................................... 176
Timing Requirements ............................................... 183
MPLAB C17.............................................................. 160
MPLAB C18.............................................................. 160
MPLAB C30.............................................................. 160
Baud Rate Setting .................................................... 110
CAN1 Register Map.................................................. 112
CAN2 Register Map.................................................. 114
Frame Types ............................................................ 105
I/O Timing Characteristics ........................................ 200
I/O Timing Requirements.......................................... 200
Message Reception.................................................. 108
Message Transmission............................................. 109
Modes of Operation .................................................. 107
Overview................................................................... 105
Characteristics.......................................................... 181
Requirements ........................................................... 181
Data EEPROM Block Erase ....................................... 52
Data EEPROM Block Write ........................................ 54
Data EEPROM Read.................................................. 51
Data EEPROM Word Erase ....................................... 52
Data EEPROM Word Write ........................................ 53
Erasing a Row of Program Memory ........................... 47
Initiating a Programming Sequence ........................... 48
Loading Write Latches ................................................ 48
NVMADR .................................................................... 46
NVMADRU ................................................................. 46
NVMCON.................................................................... 46
NVMKEY .................................................................... 46
Overview..................................................................... 11
Data Space Write Saturation ...................................... 19
Overflow and Saturation ............................................. 17
Round Logic ............................................................... 18
2
C .............................................................................. 90
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