LCMXO256C-5TN100C LATTICE SEMICONDUCTOR, LCMXO256C-5TN100C Datasheet - Page 146

• Manufacturer Part Number: LCMXO256C-5TN100C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, 256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO256C-5TN100C

• Cpld Type: FLASH
• No. Of Macrocells: 128
• No. Of I/o's: 78
• Propagation Delay: 3.5ns
• Global Clock Setup Time: 1.3ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Figure 9-23. PSEUDO DUAL PORT RAM Timing Diagram – without Output Registers
Figure 9-24. PSEUDO DUAL PORT RAM Timing Diagram – with Output Registers
Read Only Memory (ROM) – EBR Based
The EBR blocks in the MachXO devices can be configured as Read Only Memory or ROM. IPexpress allows users
to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size, as per design requirement. Users are
required to provide the ROM memory content in the form of an initialization file.
IPexpress generates the memory module as shown in Figure 9-25.
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClockEn
RdClockEn
WrAddress
RdAddress
WrClock
RdClock
WrClock
RdClock
Data
Data
Q
Q
t
t
t
t
t
SUADDR_EBR
SUADDR_EBR
SUDATA_EBR
t
SUADDR_EBR
SUADDR_EBR
SUDATA_EBR
t
t
SUCE_EBR
SUCE_EBR
Data_0
Add_0
Data_0
Add_0
t
t
t
t
t
t
HADDR_EBR
HADDR_EBR
HDATA_EBR
HADDR_EBR
HADDR_EBR
HDATA_EBR
Invalid Data
Data_1
Data_1
Add_1
Add_1
Invalid Data
9-23
t
t
SUCE_EBR
SUCE_EBR
Memory Usage Guide for MachXO Devices
Add_0
Add_0
t
t
HCE_EBR
HCE_EBR
t
CO_EBR
Data_0
Add_1
Add_1
t
COO_EBR
Data_2
Add_2
Data_2
Add_2
Data_1
Data_0
Add_2
Add_2
t
HCE_EBR
t
HCE_EBR
a_2
Dat
a_1
Dat