LCMXO256C-5TN100C LATTICE SEMICONDUCTOR, LCMXO256C-5TN100C Datasheet - Page 158

• Manufacturer Part Number: LCMXO256C-5TN100C
• Description: MACHXO PLD FLASH, SCRAM 1.8V, 256
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: MachXOr

Specifications of LCMXO256C-5TN100C

• Cpld Type: FLASH
• No. Of Macrocells: 128
• No. Of I/o's: 78
• Propagation Delay: 3.5ns
• Global Clock Setup Time: 1.3ns
• Frequency: 600MHz
• Supply Voltage Range: 1.71V To 3.465V
• Operating: RoHS Compliant

Lattice Semiconductor
Distributed ROM (Distributed_ROM) – PFU Based
PFU-based Distributed ROM is also created using the 4-input LUT (Look-Up Table) available in the PFU. These
LUTs can be cascaded to create larger distributed memory sizes.
Figure 9-37 shows the Distributed ROM module as generated by IPexpress.
Figure 9-37. Distributed ROM Generated by IPexpress
The generated module makes use of the 4-input LUT available in the PFU. Additional logic like clock and reset is
generated by utilizing the resources available in the PFU.
Ports such as Out Clock (OutClock) and Out Clock Enable (OutClockEn) are not available in the hardware primi-
tive. These are generated by IPexpress when the user wants the to enable the output registers in the IPexpress
configuration.
The various ports and their definitions are listed in Table 9-17. The table lists the corresponding ports for the mod-
ule generated by IPexpress and for the primitive.
Table 9-17. PFU-based Distributed ROM Port Definitions
Users have the option of enabling the output registers for Distributed ROM (Distributed_ROM). Figures 9-38 and 9-
39 show the internal timing waveforms for the Distributed ROM with these options.
Figure 9-38. PFU-Based ROM Timing Waveform – Without Output Registers
Generated Module
Port Name in
OutClockEn
OutClock
Address
Reset
Address
Q
Q
Invalid Data
t
OutClockEn
SUADDR_PFU
PFU Block Primitive
OutClock
Port Name in the
Address
Reset
AD[3:0]
Add_0
DO
—
—
—
t
HADDR_PFU
t
CORAM_PFU
Distributed ROM
9-35
PFU-based
Data_0
Add_1
Memory Usage Guide for MachXO Devices
Out Clock Enable
Description
Out Clock
Data Out
Address
Reset
Data_1
Add_2
Q
Rising Clock Edge
Data_2
Active State
Active High
Active High
—
—