M25P80-VMN6P NUMONYX, M25P80-VMN6P Datasheet - Page 31

• Manufacturer Part Number: M25P80-VMN6P
• Description: MEMORY, FLASH, SERIAL, 8MB, 8NSOIC
• Manufacturer: NUMONYX

Specifications of M25P80-VMN6P

• Memory Size: 8Mbit
• Clock Frequency: 75MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: NSOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Package / Case: NSOIC
• Memory Type: Flash
• Memory Configuration: 1M X 8
• Interface Type: Serial, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data Input (D). Any address inside the
Sector (see
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see
Figure 15. Sector Erase (SE) instruction sequence
1. Address bits A23 to A20 are Don’t Care.
S
C
D
Table
3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
0
Table 3
1
2
Instruction
3
and
4
Figure
5
Table
6
7
15.
MSB
2) is not executed.
23 22
8
9
24 Bit Address
2
29 30 31
1
0
AI03751D
SE
) is
31/57