PIC16LF1827-I/MV Microchip Technology, PIC16LF1827-I/MV Datasheet - Page 183
![IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC16LF1827-I/MV
Manufacturer Part Number
PIC16LF1827-I/MV
Description
IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1827-I/MV
Controller Family/series
PIC16LF
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Processor Series
PIC16LF
Core
PIC
Data Ram Size
256 B
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.7
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
20.8
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bits of the T1CON register must be
• T1OSCEN bit of the T1CON register must be
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 20-2:
2010 Microchip Technology Inc.
Note:
configured
configured
Note 1: Arrows indicate counter increments.
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
Timer1 Interrupt
Timer1 Operation During Sleep
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
TIMER1 INCREMENTING EDGE
Preliminary
20.9
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
For
“Capture/Compare/PWM Modules”.
20.10 ECCP/CCP Special Event Trigger
When any of the CCP’s are configured to trigger a spe-
cial event, the trigger will clear the TMR1H:TMR1L reg-
ister pair. This special event does not cause a Timer1
interrupt. The CCP module may still be configured to
generate a CCP interrupt.
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
Timer1 should be synchronized and F
selected as the clock source in order to utilize the Spe-
cial Event Trigger. Asynchronous operation of Timer1
can cause a Special Event Trigger to be missed.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
For more information, see Section 15.2.5 “Special
Event Trigger”.
PIC16F/LF1826/27
more
ECCP/CCP Capture/Compare Time
Base
information,
see
DS41391C-page 183
OSC
Section 23.0
/4 should be
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