PIC16LF1827-I/MV Microchip Technology, PIC16LF1827-I/MV Datasheet - Page 314
![IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28](/photos/12/13/121305/c04-152_mv_sml.jpg)
PIC16LF1827-I/MV
Manufacturer Part Number
PIC16LF1827-I/MV
Description
IC, 8BIT MCU, PIC16LF, 32MHZ, QFN-28
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Specifications of PIC16LF1827-I/MV
Controller Family/series
PIC16LF
Eeprom Memory Size
256Byte
Ram Memory Size
384Byte
Cpu Speed
32MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
Core Size
8 Bit
Program Memory Size
4kWords
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Processor Series
PIC16LF
Core
PIC
Data Ram Size
256 B
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
16
Number Of Timers
5
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC16F/LF1826/27
25.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 25.4.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
DS41391C-page 314
APFCON0
APFCON1
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISB
TXSTA
Legend:
Note 1:
never Idle
Name
*
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
Page provides register information.
PIC16F/LF1827 only.
EUSART Synchronous Slave
Reception
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
SPEN
CSRC
Bit 7
GIE
RECEPTION
—
SDO1SEL
TRISB6
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
—
SS1SEL
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART Receive Data Register
P2BSEL
TRISB4
Preliminary
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
—
(1)
CCP2SEL
ADDEN
TRISB3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
Bit 3
25.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
—
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
(1)
P1DSEL
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
Bit 2
—
—
Synchronous Slave Reception
Set-up:
P1CSEL
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
Bit 1
INTF
2010 Microchip Technology Inc.
—
CCP1SEL
TXCKSEL
TMR1IE
TMR1IF
TRISB0
ABDEN
IOCIF
RX9D
TX9D
Bit 0
Register
on Page
292*
122
122
298
101
102
105
297
129
296
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