PIC18LF8680-I/PT Microchip Technology, PIC18LF8680-I/PT Datasheet - Page 399

• Manufacturer Part Number: PIC18LF8680-I/PT
• Description: IC, 8BIT MCU, PIC18LF, 40MHZ, PLCC-64
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF8680-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 39
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 32768 Words
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Rohs Compliant: Yes
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3328 B
• Interface Type: I2C, SPI, AUSART, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
PC =
Q1
No
TOS
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
1
2
RETURN
0000
Q2
No
No
[0,1]
W,
PC,
RETURN [s]
BSR,
0000
operation
Process
Data
STATUS,
Q3
No
0001
from stack
operation
PIC18F6585/8585/6680/8680
Pop PC
Q4
No
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register ‘f’
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C, N, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
f
[0,1]
[0,1]
C
dest<0>
255
dest<n+1>,
C,
RLCF
01da
Process
REG, 0, 0
Data
Q3
register f
DS30491C-page 397
f [,d [,a]]
ffff
destination
Write to
Q4
ffff