PIC32MX360F256L-80I/BG Microchip Technology, PIC32MX360F256L-80I/BG Datasheet - Page 3
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PIC32MX360F256L-80I/BG
Manufacturer Part Number
PIC32MX360F256L-80I/BG
Description
IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX360F256L-80I/BG
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI
No. Of Pwm Channels
5
Core Size
32 Bit
Program Memory Size
256 KB
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Embedded Interface Type
EUSART, I2C, SPI
Rohs Compliant
Yes
Processor Series
PIC32MX3xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EUART, I2C, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F256L-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
I/O PORTs
Watchdog
Oscillator
Oscillator
Capture
Capture
Module
ICSP™
Timers
Timers
Timers
(WDT)
UART
UART
UART
Timer
DMA
Input
DMA
Input
PMP
PMP
USB
Only those issues indicated in the last column apply to the current silicon revision.
Asynchronous
Channel Abort
Speed Switch
Programming
16-bit Mode
Breakpoints
High-Speed
Handshake
Wait States
DMA Read
SILICON ISSUE SUMMARY (CONTINUED)
Baud Rate
Operating
Generator
Clock Out
Hardware
with DMA
Condition
Feature
Mode
Mode
Mode
—
—
—
—
—
Number
Item
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
When using the hardware assisted read-modify-write
registers, PORTxINV, PORTxSET and PORTxCLR, the
source used for the operation is the LATx register, not the
PORTx register.
The TMRx register stays at zero for two timer clock cycles
when the PRx register is 0x0000.
The timer prescaler may not be reset correctly when it is
used with a slow external clock.
The Timer1 prescaler may not be reset correctly when it is
used with a slow external clock.
The CTS pin does not deassert until at least 2 bytes are
free in the UART FIFO.
An incorrect WDT Time-out Reset may occur.
DMA channel abort on a channel that is not currently
active may have unintended effects on other active
channels.
The Primary Oscillator Circuit (P
XTPLL, HS and HSPLL modes, does not operate over the
voltage and temperature range that is listed as item D5 in
the device data sheet.
The WAITE field in PMMODE<1:0> does not add a Wait
state to PMP master reads when it is programmed to the
value ‘01’.
Using BRG values of 0, 1 or 2 cause the Start bit to be
shortened.
16-bit DMA transfers from the ICAP module FIFO buffer
do not advance the ICAP FIFO pointer.
The USB module does not correctly switch from full-speed
to low-speed after sending a PRE packet to a hub.
The DMA buffer may be erroneously filled with the last
data read prior to the breakpoint.
Events can be missed if the PMDIN register is used as the
DMA source or destination and the PMP IRQ is used as
the DMA trigger.
When in 16-bit mode, the upper 16 bits of the 32-bit
ICxBUF register contain Timer3 values.
When programming the PIC32 using the 2-wire PGC and
PGD pins, programming data appears as an output on the
JTAG TDO pin.
In BRGH = 1 mode, the received data is not sampled in
the middle of the bit.
A clock signal is present on the CLKO pin, regardless of
the clock source and setting of the CLOCKOUT
Configuration bit, under certain conditions.
Issue Summary
PIC32MX3XX/4XX
OSC
), when using XT,
B2 B3 B4 B6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DS80440D-page 3
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X