AT80C51RD2-3CSUM Atmel, AT80C51RD2-3CSUM Datasheet - Page 52

• Manufacturer Part Number: AT80C51RD2-3CSUM
• Description: IC, 8BIT MCU, 80C51, 40MHZ, DIP-40
• Manufacturer: Atmel

Specifications of AT80C51RD2-3CSUM

• Controller Family/series: 80C51
• No. Of I/o's: 32
• Ram Memory Size: 1280Byte
• Cpu Speed: 40MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 5
• Digital Ic Case Style: DIP
• Core Size: 8 Bit
• Rohs Compliant: Yes
• Processor Series: AT80x
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 1280 B
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIL-40
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• Cpu Family: AT80
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 1.25KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 40
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. Keyboard Interface
13.0.1
13.0.2
52
AT80C51RD2
Interrupt
Power Reduction Mode
The AT80C51RD2 implement a keyboard interface allowing the connection of a 8 x n matrix key-
board. It is based on 8 inputs with programmable interrupt capability on both high or low level.
These inputs are available as alternate function of P1 and allow to exit from idle and power-
down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS, the Key-
board Level Selection register (Table 13-3), KBE, The Keyboard Interrupt Enable register
(Table 13-2), and KBF, the Keyboard Flag register (Table 13-1).
The keyboard inputs are considered as 8 independent interrupt sources sharing the same inter-
rupt vector. An interrupt enable bit (KBD in IE1) allows global enable or disable of the keyboard
interrupt (see Figure 13-1). As detailed in Figure 13-2 each keyboard input has the capability to
detect a programmable level according to KBLS.x bit value. Level detection is then reported in
interrupt flags KBF.x that can be masked by software using KBE.x bits.
This structure allow keyboard arrangement from 1 x n to 8 x n matrix and allows usage of P1
inputs for other purpose.
Figure 13-1. Keyboard Interface Block Diagram
Figure 13-2. Keyboard Input Circuitry
P1 inputs allow exit from idle and power-down modes as detailed in Section “Power-down
Mode”, page 56.
P1:x
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
V
CC
Internal Pull-up
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
Input Circuitry
KBLS.x
0
1
KBF.x
KBE.x
KBD
IE1
Keyboard Interface
Interrupt Request
KBDIT
4113D–8051–01/09