CS61574A-IL1Z Cirrus Logic Inc, CS61574A-IL1Z Datasheet

Page 1

... Host Mode Extended Hardware Mode Cirrus Logic, Inc. Crystal Semiconductor Corporation http://www.cirrus.com T1/E1 Line Interface General Description Applications • • • ORDERING INFORMATION Copyright ¤ Cirrus Logic, Inc. 2009 © (All Rights Reserved) CS61574A CS61575 1 ...

Page 2

... ABSOLUTE MAXIMUM RATINGS Parameter RECOMMENDED OPERATING CONDITIONS Parameter DIGITAL CHARACTERISTICS Parameter μ 2 CS61574A CS61575 Symbol Min Symbol Min Typ ° ° ± Symbol Min Typ μ Max Units ° ° Max Units ° Max Units ± μ DS154F3 ...

Page 3

... ANALOG SPECIFICATIONS Parameter Transmitter Ω Ω Driver Performance Monitor μ Ω DS154F3 ° ° Min Ω Ω Ω Ω CS61574A CS61575 ± Typ Max Units Ω Ω Ω Ω Ω 3 ...

Page 4

... ANALOG SPECIFICATIONS Parameter Receiver 4 ° ° ± Min Typ CS61574A CS61575 Max Units Ω DS154F3 ...

Page 5

... ANALOG SPECIFICATIONS Parameter Jitter Attenuator DS154F3 ° ° ± Min Typ CS61574A CS61575 Max Units 5 ...

Page 6

... T1 SWITCHING CHARACTERISTICS Parameter E1 SWITCHING CHARACTERISTICS Parameter 6 CS61574A CS61575 ° ° ± Symbol Min Typ ° ° ± Symbol Min Typ Max Units Max Units DS154F3 ...

Page 7

... SWITCHING CHARACTERISTICS Parameter Figure 2. Recovered Clock and Data Switching Characteristics DS154F3 ° ° Symbol Figure 1. Signal Rise and Fall Characteristics CS61574A CS61575 ± Min Typ Max Units 7 ...

Page 8

... Figure 3a. Transmit Clock and Data Switching Characteristics Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram 8 Figure 3b. Alternate External Clock Characteristics Figure 4. Serial Port Write Timing Diagram Figure 5. Serial Port Read Timing Diagram CS61574A CS61575 DS154F3 ...

Page 9

... The CS61575 is optimized to attenuate large amplitude, low frequency jitter for T1 Customer Premises Equipment (CPE) applica- tions as required by AT&T 62411. The CS61574A is optimized to minimize data delay in T1 and E1 switching or transmission applications. Refer to the "Jitter Attenuator" section for addi- tional information. ...

Page 10

... HARDWARE MODE CS61575 CS61574A EXTENDED HARDWARE MODE CS61575 CS61574A HOST MODE CS61575 CS61574A Figure 7. Overview of Operating Modes CS61574A CS61575 DS154F3 ...

Page 11

... Table 3. Line Length Selection DS154F3 Figure 8. Typical Pulse Shape at DSX-1 Cross Connect The CS61575 and CS61574A line drivers are de- signed to drive a 75 Ω equivalent load. For E1 applications, the CS61574A and CS61575 drivers provide return loss during the transmission of both marks and spaces. This im- proves signal quality by minimizing reflections off the transmitter ...

Page 12

... LEN2/1/0=0/0/0. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. The CS61574A and CS61575 will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 ...

Page 13

... In effect, the 13 phases are analogous MHz clock when the reference clock is 1.544 MHz. This implementation utilizes the benefits MHz clock for clock recovery without actually having the clock present to im- pede analog circuit performance. Figure 11. Minimum Input Jitter Tolerance of Receiver CS61574A CS61575 13 ...

Page 14

... G.742. A typical jitter attenuation curve is shown in Figure 12. The CS61575 fully meets AT&T 62411 jitter attenuation requirements. The CS61574A will have a discontinuity in the jitter transfer function when the incoming jitter ampli- tude exceeds approximately 23 UIs. The jitter attenuator works in the following man- ner ...

Page 15

... During this activity, data will never be lost. The difference between the CS61575 and CS61574A is the depth of the FIFO in the jitter attenuator. The CS61575 has a 192-bit FIFO which allows it to attenuate large amplitude, low frequency jitter as required by AT& ...

Page 16

... IC monitor performance of a neigh- boring IC, rather than having it monitor its own performance. Note that a CS61574A or CS61575 can not be used to monitor a CS61574 due to out- put stage differences. Line Code Encoder/Decoder In the Extended Hardware Mode, three line codes are available: AMI, B8ZS and HDB3 ...

Page 17

... However, a reset function is available which will clear all registers. DS154F3 CS61574A CS61575 In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP) ...

Page 18

... SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in appli- cations where the host processor has a bi-directional I/O port. Table 11. Output Data Bits CS61574A CS61575 DS154F3 ...

Page 19

... A 68 μF tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. DS154F3 CS61574A CS61575 Schematic & Layout Review Service ...

Page 20

... LLOOP TPOS RLOOP TNEG LEN2 MODE LEN1 RNEG LEN0 RPOS RGND RCLK RV+ XTALIN RRING XTALOUT RTIP DPM MRING LOS MTIP TTIP TRING TGND TV+ DPM LOS TTIP CS61574A CS61575 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+ DS154F3 ...

Page 21

... TDATA RLOOP TCODE LEN2 MODE LEN1 BPV LEN0 RDATA RGND RCLK RV+ XTALIN RRING XTALOUT RTIP AIS PCS LOS RCODE TTIP TRING TGND TV+ BPV AIS LOS TTIP CS61574A CS61575 TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+ 21 ...

Page 22

... CLKE TCLK SCLK TPOS CS TNEG SDO MODE SDI RNEG INT RPOS RGND RCLK RV+ XTALIN RRING XTALOUT RTIP DPM MRING LOS MTIP TTIP TRING TGND TV+ DPM LOS TTIP CS61574A CS61575 CLKE SCLK CS SDO SDI INT RGND RV+ RRING RTIP MRING MTIP TRING TV+ DS154F3 ...

Page 23

... INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. DS154F3 CS61574A CS61575 23 ...

Page 24

... Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. 24 CS61574A CS61575 DS154F3 ...

Page 25

... Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. DS154F3 CS61574A CS61575 25 ...

Page 26

... These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor. Ordering Guide Model Frequency FIFO Depth (Bits CS61574A CS61575 Package , Lead-free 2 , Lead-free DS154F3 ...

Page 27

... DS154F3 DIM MIN 28 pin A Plastic DIP ∝ L ∝ 28-pin PLCC 28 MILLIMETERS DIM MIN NOM MAX D/E D1/E1 D2/E2 e CS61574A CS61575 MILLIMETERS INCHES NOM MAX MIN NOM MAX INCHES MIN NOM MAX 27 ...

Page 28

... This capacitor is needed to prevent any output stage imbalance from resulting current through the transformer primary. This current might satu- rate the transformer producing an output offset level shift. CS61574A CS61575 Ω μ μ Crystal XTL 6.176 MHz 8 ...

Page 29

... Figure A2. 120 Ω, E1 Hardware Mode Configuration Figure A3. 75 Ω, E1 Extended Hardware Mode Configuration DS154F3 μ μ μ CS61574A OR CS61575 IN HARDWARE MODE μ μ μ CS61574A OR CS61575 IN EXTENDED HARDWARE MODE CS61574A CS61575 μ μ 29 ...

Page 30

... Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61574A and CS61575. Refer to the "Telecom Transformer Se- lection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer ...

Page 31

... Pulse Engineering PE-65766 Bel Fuse S553-0013-07 Pulse Engineering PE-65835 Pulse Engineering PE-65839 Table A3. Recommended Transformers Figure A4. Interfacing the CS61574A or CS61575 CS61574A CS61575 Package Type 1.5 kV through-hole, single 1.5 kV through-hole, single 1.5 kV through-hole, single 1.5 kV through-hole, dual 1.5 kV through-hole, dual 1.5 kVsurface-mount, dual 1 ...

Page 32

Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for frequency pullability. The crystal oscillation frequency is dictated by capacitive loading, which is con- trolled by the chip. Therefore, the crystals must meet the following specifications. Total ...

Page 33

F3 Jul ’09 Removed development system info. (No longer supported). Removed PDIP option. Changed PLCC package option to lead-free. ...

Page 34

For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. ...