CS61574A-IL1Z Cirrus Logic Inc, CS61574A-IL1Z Datasheet - Page 17

• Manufacturer Part Number: CS61574A-IL1Z
• Description: IC T1/E1 Ln Intrfc Unit F/Stratum-4 Apps
• Manufacturer: Cirrus Logic Inc

Specifications of CS61574A-IL1Z

• Ic Interface Type: Serial
• Supply Voltage Range: 4.75V To 5.25V
• Power Dissipation Pd: 290mW
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LCC
• No. Of Pins: 28
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Alarm Indication Signal
In the Extended Hardware Mode, the receiver sets
the output pin AIS high when less than 9 zeros
are detected out of 8192 bit periods. AIS returns
low when 9 or more zeros are detected out of
8192 bit periods.
Parallel Chip Select
In the Extended Hardware Mode, PCS can be
used to gate the digital control inputs: TCODE,
RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP
and TAOS. Inputs are accepted on these pins only
when PCS is low and will immediately change
the operating state of the device. Therefore, when
cycling PCS to update the operating state, the
digital control inputs should be stable for the en-
tire PCS low period. The digital control inputs are
ignored when PCS is high.
Power On Reset / Reset
Upon power-up, the IC is held in a static state
until the supply crosses a threshold of approxi-
mately 3 Volts. When this threshold is crossed,
the device will delay for about 10 ms to allow the
power supply to reach operating voltage. After
this delay, calibration of the delay lines used in
the transmit and receive sections commences. The
delay lines can be calibrated only if a reference
clock is present. The reference clock for the re-
ceiver is provided by the crystal oscillator, or
ACLKI if the oscillator is disabled. The reference
clock for the transmitter is provided by TCLK.
The initial calibration should take less than
20 ms.
In operation, the delay lines are continuously cali-
brated, making the performance of the device
independent of power supply or temperature vari-
ations. The continuous calibration function
forgoes any requirement to reset the line interface
when in operation. However, a reset function is
available which will clear all registers.
DS154F3
In the Hardware and Extended Hardware Modes,
a reset request is made by simultaneously setting
both the RLOOP and LLOOP pins high for at
least 200 ns. Reset will initiate on the falling edge
of the reset request (falling edge of RLOOP and
LLOOP). In the Host Mode, a reset is initiated by
simultaneously writing RLOOP and LLOOP to
the register. In either mode, a reset will set all reg-
isters to 0 and force the oscillator to its center
frequency before initiating calibration. A reset
will also set LOS high.
Serial Interface
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
on-board register can be written to via the SDI
pin or read from via the SDO pin at the clock rate
determined by SCLK. Through this register, a
host controller can be used to control operational
characteristics and monitor device status. The se-
rial port read/write timing is independent of the
system transmit and receive timing.
Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
Address and input data bits are clocked in on the
rising edge of SCLK. The clock edge on which
output data is stable and valid is determined by
CLKE as shown in Table 5. Data transfers are ter-
minated by setting CS high. CS may go high no
sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 1, data
bit D7 is held until the falling edge of the 16th
clock cycle. When CLKE = 0, data bit D7 is held
until the rising edge of the 17th clock cycle. SDO
goes High-Z after CS goes high or at the end of
the hold period of data bit D7.
CS61574A CS61575
17