CS61574A-IL1Z Cirrus Logic Inc, CS61574A-IL1Z Datasheet - Page 18

• Manufacturer Part Number: CS61574A-IL1Z
• Description: IC T1/E1 Ln Intrfc Unit F/Stratum-4 Apps
• Manufacturer: Cirrus Logic Inc

Specifications of CS61574A-IL1Z

• Ic Interface Type: Serial
• Supply Voltage Range: 4.75V To 5.25V
• Power Dissipation Pd: 290mW
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LCC
• No. Of Pins: 28
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An address/command byte, shown in Table 9, pre-
cedes a data register. The first bit of the
address/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The line interface responds to address
16 (0010000). The last bit is ignored.
The data register, shown in Table 10, can be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver.
18
Table 9. Address/Command Byte
Table 10. Input Data Register
Figure 13. Input/Output Timing
Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
Output data from the serial interface is presented
as shown in Tables 11 and 12. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(Bits 5, 6 and 7) indicate intermittent loss of sig-
nal and/or driver problems.
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
cations where the host processor has a
bi-directional I/O port.
1) The current interrupt on the serial interface
2) Output data bits 5, 6 and 7 will be reset as
3) Future interrupts for the corresponding LOS
will be cleared. (Note that simply reading
the register bits will not clear the inter-
rupt).
appropriate.
or DPM will be prevented from occurring.
Table 11. Output Data Bits 0 - 4
CS61574A CS61575
DS154F3