MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 3

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MCIMX535DVV1C

Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MCIMX535DVV1C

Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed

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1.1
Table 1
1.2
The i.MX53xD multimedia applications processor (AP) is based on the ARM Platform, which has the
following features:
The memory system consists of the following components:
Freescale Semiconductor
1
2
PCIMX535DVV1B
PCIMX538DZK1B
Part numbers with a PC prefix indicate non production engineering parts.
Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.
Part Number
MMU, L1 instruction and L1 data cache
Unified L2 cache
Target frequency of the core (including Neon, VFPv3 and L1 cache): 1 GHz
Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite)
coprocessor supporting VFPv3
TrustZone
Level 1 cache:
— Instruction (32 Kbyte)
— Data (32 Kbyte)
Level 2 cache:
— Unified instruction and data (256 Kbyte)
Level 2 (internal) memory:
— Boot ROM, including HAB (64 Kbyte)
— Internal multimedia/shared, fast access RAM (128 Kbyte)
— Secure/non-secure RAM (16 Kbyte)
External memory interfaces:
— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte
— 32bit LPDDR2
— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC
— 8,16-bit NOR Flash, PSRAM & cellular RAM.
provides ordering information.
Ordering Information
Features
1
Mask
N78C
N78C
Set
i.MX53xD Applications Processors for Consumer Products, Rev. 1
1 GHz, full feature set
1 GHz, full feature set
Table 1. Ordering Information
Features
Temperature
Range (
-20 to +85
-20 to +85
Case
°
C)
19 x 19 mm, 0.8 mm pitch BGA
Case TEPBGA-2
12x12 0.4P PoP
Package
2
Introduction
3

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