MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet
MCIMX535DVV1C
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... The flexibility of the i.MX53xD architecture allows for its use in a wide variety of applications. As the heart of This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX53CEC Rev. 3, 7/2011 MCIMX53xD ...
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... Freescale representative. The i.MX53xD application processor is a follow-on to the i.MX51, with improved performance, power efficiency, and multimedia capabilities. i.MX53xD Applications Processors for Consumer Products, Rev ® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s, and 2 S serial audio, among others). Freescale Semiconductor ...
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... Ordering Information Table 1 provides ordering information. 1 Part Number Mask Set PCIMX535DVV1C N78C MCIMX535DVV1C N78C PCIMX538DZK1C N78C MCIMX538DZK1C N78C 1 Part numbers with a PC prefix indicate non production engineering parts. 2 Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3. 1.2 Features The i.MX53xD multimedia applications processor (AP) is based on the ARM Platform, which has the following features: • ...
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... Hard disk drives: — PATA U-DMA mode 5, 100 MByte/s — SATA I, 1.5 Gbps • Displays: — Five interfaces available. Total rate of all interfaces 180 Mpixels/s, 24 bpp two interfaces may be active at once. i.MX53xD Applications Processors for Consumer Products, Rev NOTE Freescale Semiconductor ...
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... Power gating SRPG (State Retention Power Gating) for ARM core and Neon • Support for various levels of system power modes • Flexible clock gating control scheme • On-chip temperature monitor • On-chip oscillator amplifier supporting 32.768 kHz external crystal i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Introduction 5 ...
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... SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization The actual feature set depends on the part number as described in Functions such as video hardware acceleration with 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. i.MX53xD Applications Processors for Consumer Products, Rev NOTE Table 1. Freescale Semiconductor ...
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... Audio, Power Mngmnt. Ethernet 10/100 Mbps IrDA XVR The numbers in brackets indicate number of module instances. For example, PWM (2) indicates two separate PWM peripherals. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor NOR/NAND Battery Ctrl Camera LVDS Camera Flash Device (2) (WSXGA+) (2) ...
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... The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. Table 2 describes these Freescale Semiconductor ...
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... Connectivity Audio Interface Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Brief Description The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). ...
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... EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO 11898), which supports both standard and extended message frames at 1 Mbps. Freescale Semiconductor ...
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... IC Identification Security Module i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Brief Description These modules are used for general purpose input/output to external ICs. Each GPIO module supports bits of I/O. Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register ...
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... The on-chip memory controller (OCRAM) module interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. Supports secure and regular boot modes. The ROM controller supports ROM patching. Freescale Semiconductor ...
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... Memory Access Control Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Brief Description Protecting read only data from modification is one of the basic elements in trusted platforms. The run-time integrity checker, version 3 (RTIC) block is a data-monitoring device responsible for ensuring that the memory content is not corrupted during program execution ...
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... Each SSI has two pairs FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two time slots are being used simultaneously. Freescale Semiconductor ...
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... USB USB Controller Connectivity Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Brief Description The IEEE 1588-2002 (version 1) standard defines a precision time protocol (PTP) - which is a time-transfer protocol that enables synchronization of networks (for example, Ethernet high degree of accuracy and precision ...
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... still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. Provides a crystal oscillator amplifier that supports a 24-MHz external crystal Provides a crystal oscillator amplifier that supports a 32.768-kHz external crystal Freescale Semiconductor ...
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... Operating Ranges table is not implied. Parameter Description Peripheral Core Supply Voltage ARM Core Supply Voltage i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Section 6, “Package Information and Contact NOTE Table 3. i.MX53xD Chip-Level Conditions CAUTION Table 4 may affect reliability or cause Table 4 ...
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... Min Max Unit –0.5 3.6 V –0.5 3.3 V — 5. –0.3 3. –0.5 OVDD +0 — 2000 — 500 o –40 150 C Symbol Value Unit R 28 °C/W θ °C/W θ °C/W θJMA R 13 °C/W θJMA R 6 °C/W θ °C/W θJC Ψ 4 °C/W JT Freescale Semiconductor ...
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... Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 7 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Board Symbol 2, 3 Single layer board R ...
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... Freescale Semiconductor Unit ...
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... LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Parameter Minimum 1.65 2 ...
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... Applications Processors for Consumer Products, Rev Table 8. External Input Clock Frequency Symbol Min f — 32.768 ckil f , See Table 33, "CAMP Electrical Parameters (CKIH1, ckih1 f CKIH2)," on page 47 ckih2 f 22 xtal Typ Max Unit 2 /32.0 — kHz MHz 24 27 MHz Freescale Semiconductor ...
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... NVCC_EIM_MAIN NVCC_EIM_SEC NVCC_EMI_DRAM NVCC_FEC NVCC_GPIO NVCC_JTAG NVCC_KPAD NVCC_LCD NVCC_LVDS i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 9. Maximal Supply Currents Conditions 1000 MHz ARM clock. Fuse Write Mode operation 1.8v (DDR2) 1.5v (DDR3) 1.2v (LPDDR2) Use maximal IO Eq Use maximal IO Eq ...
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... F) - Data change rate 0.5 of the clock rate (F). i.MX53xD Applications Processors for Consumer Products, Rev Conditions Max Current Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Unit N=2 Freescale Semiconductor ...
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... Otherwise, it has to be powered ON together with VCC, or preceding VCC. •The VCC should be powered ON together, or any time after NVCC_SRTC_POW. •NVCC_CKIH should be powered ON after VCC is stable and before other IO supplies (NVCC_xxx) are powered ON. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Conditions Typical at 25 °C RX 5.5 ...
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... ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other. The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. i.MX53xD Applications Processors for Consumer Products, Rev NOTE Freescale Semiconductor ...
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... V supply (for example, from the parts that use both 1.8 V and the 3.3 V supply fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 90% 90% Δt > 0 90% Δ ...
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... Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes • Low Voltage I/O (LVIO) • Ultra High Voltage I/O (UHVIO) • LVDS I/O i.MX53xD Applications Processors for Consumer Products, Rev Table 7 Ultra High voltage I/O (UHVIO) supplies , . A deviation of few ) Section 6, Freescale Semiconductor ...
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... Low-level output voltage High-level output current (1.1-1.3V OVDD) Low-level output current (1.1-1.3V OVDD) High-level output current (1.65-3.1V OVDD) i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor NOTE Table Symbol Test Conditions Voh Iout = –1 mA Iout= specified Ioh Drive Vol Iout = 1 mA Iout= specified Iol Drive × ...
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... OVDD — — × — — 0.5 OVDD — — 2 — — 161 2 — — — — — — — 130 — Table 7, unless otherwise noted. Freescale Semiconductor Unit μA μA μA μA μA kΩ ...
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... The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009. Table 13. LPDDR2 I/O DC Electrical Parameters Parameters High-level output voltage Low-level output voltage Input Reference Voltage DC input High Voltage DC input Low Voltage i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol Test Conditions Voh — 0.9*OVDD Vol — Ioh OVDD=1.7 V, – ...
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... OVSS — Vref-0.1 0.2 — See Note 3 See Note — -0.2 — — 0.4 — — 0.67 0.49*OVDD Vref 0.51*OVDD — — 1 — — 1 — — 3 — — — 130 — Freescale Semiconductor 2 μA % Ohm kΩ Unit μA Ω Ω kΩ ...
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... Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled. 4 Use an off-chip pull resistor of less than 60 kΩ to override this keeper. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 15. LVIO DC Electrical Characteristics Symbol Test Conditions Vih — ...
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... OVDD 0.3 × OVDD 0 — — 0.43 1.33 — — 0.5 × OVDD — — — — 1 — — 202 1 — — — — — — 1 5.7 4 — 130 — Freescale Semiconductor μA μA μA μA μA kΩ ...
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... Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol Test Conditions V Rload=100Ω ...
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... Vovdd – Vref2 Figure 4. Impedance Matching Load for Measurement i.MX53xD Applications Processors for Consumer Products, Rev OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × Ztl Cload = 1p Vin (do) t,(ns) Vout (pad) t,(ns) Freescale Semiconductor ...
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... The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 18. GPIO Output Buffer Impedance Test Conditions ...
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... Applications Processors for Consumer Products, Rev Drive strength (DSE) 000 001 010 Hi-Z 300 150 3 Hi-Z 180 90 3 Hi-Z 200 100 3 Hi-Z 140 70 3 Hi-Z 160 Hi-Z 240 120 3 Hi-Z 160 Hi-Z 240 120 3 1 011 100 101 110 111 100 Freescale Semiconductor Unit Ω ...
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... Low Voltage I/O (LVIO) • Ultra High Voltage I/O (UHVIO) • LVDS I/O The load circuit and output transition time waveforms are shown in Output (at pad) i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 20. UHVIO Output Buffer Impedance Min OVDD OVDD 1. ...
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... Min Typ Max — — 1.45/1.24 2.76/2.54 — — 1.81/1.59 3.57/3.33 — — 2.54/2.29 5.25/5.01 Freescale Semiconductor Unit V/ns mA/ns ns Unit ...
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... Output AC differential cross point voltage Single output slew rate Skew between pad rise/fall asymmetry + skew caused by SSN 1 Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this document. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Test Symbol Condition tr tps ...
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... Min Typ Max — OVDD Vref 0.175 0 — – 0.35 — — 0.15 – — Vref + 0.15 Freescale Semiconductor Unit V*ns V/ns ns Unit ...
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... IOMUXC control registers. Table 26. LVIO I/O AC Parameters in Slow Mode Parameter 1 Input Transition Times 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol Test Condition 4 Vref Vox(ac) — Ω to Vref tsr ...
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... Min Typ Max — — 1.72/1.92 3.46/3.70 — — 2.38/2.56 5.07/5.25 — — 4.55/4.58 10.04/9.94 Freescale Semiconductor Unit ns Unit ns V/ns mA/ns ns Unit ns ...
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... Table 30. AC Electrical Characteristics of LVDS Pad Parameter 1 Transition Low to High Time 1 Transition High to Low Time Operating Frequency Offset voltage imbalance 1 Measurement levels are 20-80% from output voltage. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol Test Condition tps tps tps 15 pF ...
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... CC1 Figure 8. Reset Timing Diagram Table 31. Reset Timing Parameters Parameter Table 32 lists the timing parameters. CC5 Figure 9. WATCHDOG_RST Timing Diagram Parameter NOTE is one period or approximately 30 μs. CKIL Min Max Unit 50 — ns Min Max Unit 1 — T CKIL Freescale Semiconductor ...
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... DPLL for PDF and MFD. 3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be zero. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Min 8.0 0 NVCC_CKIH – 0.25 ...
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... Table 35. NFC Clock Settings Examples enfc_clk (MHz NOTE (RE_B high to output hold) period. Setting the rhoh > also recommended that the rhoh Figure 15, and Table 36 show the default Figure 15, and Table 36 show symmetric T-Clock Period (ns) 14.29 70 33.33 30 33. 44.33 22 Freescale Semiconductor ...
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... NFCLE NFCE_B NFWE_B NFIO[7:0] NFCE_B NFWE_B NFALE NFIO[7:0] i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor (RE_B high to output high-Z). In most devices, the rhz NF1 NF3 NF5 NF8 NF9 command Figure 10. Command Latch Cycle Timing ...
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... Figure 14. Read Data Latch Timing, Symmetric Mode i.MX53xD Applications Processors for Consumer Products, Rev NF3 NF10 NF11 NF5 NF8 NF9 Data to NF Figure 12. Write Data Latch Timing NF14 NF15 NF13 NF16 NF17 NF12 Data from NF NF14 NF15 NF13 NF16 Data from NF NF18 Freescale Semiconductor ...
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... NFCLE NFCE_B NFWE_B NFRE_B NFRB_B i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor NF19 NF20 NF21 NF22 Figure 15. Other Timing Parameters Electrical Characteristics 51 ...
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... T — 0.5T – 1.15 — 11.2 – Tdl — — 2T aclk 2 Tdl – 11.2 2T aclk 9T — T – 3. 0.3 10.5T — — Data propogation delay from I/O pad to Dpd 1.5T – REA = DSR ). Default aclk is aclk Freescale Semiconductor + ...
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... EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some of the modes the EIM and the NAND FLASH have shared data bus. pads allocation in different modes. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor value that can be used with NFC. RHZ 2 Tdl – ...
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... DSZ = 001 DSZ = 011 EIM_DA EIM_DA EIM_DA [15:0] [15:0] [15:0] EIM_A EIM_A NANDF_D 1 1 [24:16] [25:16] [8:0] NANDF_D EIM_DA EIM_DA [7:0] [7:0] [7:0] NANDF_D EIM_DA EIM_DA [15:8] [15:8] [15:8] EIM_D — NANDF_D [23:16] [7:0] EIM_D — NANDF_D [31:24] [15:8] Freescale Semiconductor ...
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... ID Parameter Min 2 WE1 BCLK Cycle time t WE2 BCLK Low Level 0.4*t Width i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor specify the timings related to the EIM module. All EIM output control WE2 WE1 WE4 WE6 WE8 WE10 WE12 WE14 WE16 Figure 16 ...
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... Freescale Semiconductor Max — — — — ...
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... BCLK ADDR Last Valid Address CSx_B WE_B ADV_B OE_B BEy_B DATA Figure 18. Synchronous Memory Read Access, WSC=1 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor ≤ 104 MHz. If BCD = 1, then 133 MHz is WE4 Address v1 WE6 WE14 WE15 WE10 WE12 WE18 ...
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... Applications Processors for Consumer Products, Rev WE4 Address V1 WE6 WE8 WE14 WE15 WE12 WE16 WE16 WE5 WE4 Address V1 Last WE6 WE8 WE15 WE14 WE10 ADH=1 NOTE WE5 WE7 WE9 WE13 WE17 D(V1) WE17 Write Data WE7 WE9 WE11 Freescale Semiconductor ...
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... Asynchronous read and write access length in cycles may vary from what is shown in Figure 25 as RWSC, OEN, and CSN is configured differently. Refer to i.MX53xD RM for the EIM programming model. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor WE4 WE5 Address V1 WE6 WE15 ...
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... Applications Processors for Consumer Products, Rev start of access WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 MAXDI start of access MAXDI WE31 Addr. V1 WE32A WE40A WE39 WE35A WE37 end of access WE32 Next Address WE40 WE36 WE38 WE44 end of access D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
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... BEy_B DATA Figure 24. Asynchronous Memory Write Access CSx_B ADDR/ M_DATA WE_B ADV_B OE_B BEy_B Figure 25. Asynchronous A/D Muxed Write Access i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE41 WE31 D(V1) Addr. V1 WE32A ...
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... WE35 WE37 D(V1) WE43 WE47 Figure 26. DTACK Read Access (DAP=0) WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE47 Figure 27. DTACK Write Access (DAP=0) WE32 Next Address WE40 WE36 WE38 WE44 WE48 WE32 Next Address WE34 WE40 WE46 WE42 WE48 Freescale Semiconductor ...
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... CSx_B Valid to Output Data Valid WE41 CSx_B Valid to Output Data A Valid (muxe d A/D) WE42 Output Data Invalid to CSx_B Invalid i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Determination by Synchronous measured 12 parameters 3 WE4 - WE6 - CSA 4 WE7 - WE5 - CSN WE4 - WE7 + (ADVN + ...
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... WE12 - WE6 + (WBEA - CSA) WE7 - WE13 + (WBEN - CSN) MAXCO - MAXCSO + MAXCO - MAXDTI MAXCSO + MAXDTI 0 Table 39 Max (If 133 Mhz is Min supported by SOC) — — — — — — - — MAXDI 0 — — (WBEA - CSA) — (WBEN - CSN) — — — 0 — Freescale Semiconductor Unit — ...
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... Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3 Table 41. DDR SDRAM Timing Parameter Table ID Parameter DDR1 SDRAM clock high-level width DDR2 SDRAM clock low-level width i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor DDR4 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Symbol ...
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... LP3 LP4 LP4 Symbol (continued) SDCLK = 400 MHz Units Min Max 0.6 — ns 0.6 — ns 0.6 — ns 0.6 — ns LP1 LP2 LP3 1 2 SDCLK = 400 MHz Units Min Max 0.45 0. 0.45 0. 0.3 — ns 0.3 — ns 0.3 — ns 0.3 — ns Freescale Semiconductor ...
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... To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window. Figure 31 and Table 44 show the data read timing parameters. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor DDR22 DDR18 DDR17 Data Data Data ...
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... Applications Processors for Consumer Products, Rev DATA DATA DATA DATA DDR26 Table 44. DDR SDRAM Read Cycle Parameter Table DATA DATA DATA DATA 1 SDCLK = 400 MHz Symbol Min Max — 0.6 — — 0.425 — — 0.275 0.475 45. Freescale Semiconductor Unit ...
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... LOAD CS8 MISO Setup Time i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 45. CSPI Nomenclature and Routing GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC DISP0_DAT, CSI0_DAT and EIM through IOMUXC DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC ...
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... ECSPI master mode timing Symbol t clk RISE/FALL t CSLH t SCS t HCS = 20 pF) t LOAD PDmosi t Smiso Max Unit — ns — ns CS5 CS6 CS4 Min Max Unit 30 — — — — ns Half SCLK period — — — ns -0.5 2.5 ns 8.5 — ns Freescale Semiconductor ...
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... Table 49. Enhanced Serial Audio Interface (ESAI) Timing Characteristics No Clock cycle 63 Clock high period • For internal clock • For external clock i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol t Hmiso t SDRY Parameters” Table 48 lists the ECSPI slave mode timing Symbol t ...
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... Freescale Semiconductor 4 Unit ...
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... Periodically sampled and not 100% tested. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 1 2,3 ’ Symbol Expression — ...
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... Electrical Characteristics 63 SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX53xD Applications Processors for Consumer Products, Rev First Bit Figure 34. ESAI Transmitter Timing 83 87 Last Bit 91 Freescale Semiconductor ...
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... SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor First Bit Figure 35. ESAI Receiver Timing Electrical Characteristics 70 72 Last Bit 75 75 ...
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... SCK SD3 CMD SD6 DAT0 DAT1 ...... DAT7 SD7 SD8 CMD DAT0 DAT1 ...... DAT7 Figure 36. SD/eMMC4.3 Timing Card Input Clock SD1 Symbols Min Max 400 25/ 20/ 100 400 — — — 3 TLH t — 3 THL t – Freescale Semiconductor Unit kHz MHz MHz kHz ...
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... Clock Frequency (MMC Full Speed/High Speed) eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD2 eSDHC Output Delay eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor – 50 MHz. – 52 MHz. Table 51 lists the eMMC4.4 timing characteristics. Be aware ...
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... Applications Processors for Consumer Products, Rev Symbols t ISU t IH Table 52 lists the MII receive channel signal timing Table 52. MII Receive Signal Timing 1 2 Min Max Unit 2.5 — ns 2.5 — ns Min Max Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor ...
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... FEC_TX_CLK pulse width high M8 FEC_TX_CLK pulse width low 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Figure 39 Table 53. Table 53. MII Transmit Signal Timing ...
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... Table 54. MII Async Inputs Signal Timing 1 M9 Figure 40. MII Async Inputs Timing Diagram Figure 41 Table 55. MII Transmit Signal Timing 1 Characteristics M8 Figure 40 shows MII asynchronous Min Max Unit 1.5 — FEC_TX_CLK period shows MII serial management channel Min Max Unit 0 — ns — — ns Freescale Semiconductor ...
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... The RMII mode timings are shown in No. M16 REF_CLK(FEC_TX_CLK) pulse width high M17 REF_CLK(FEC_TX_CLK) pulse width low M18 REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 1 Characteristics M14 M12 M13 Table 56 and Figure 42. Table 56. RMII Signal Timing ...
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... Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX53xD Applications Processors for Consumer Products, Rev Table 56. RMII Signal Timing (continued) 1 Characteristics M16 M18 M19 M20 M21 Min Max Unit 4 — — ns M17 Freescale Semiconductor ...
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... If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released total capacitance of one bus line in pF. b i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 2 C module module timing characteristics. IC11 IC10 IC7 ...
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... Y[1] Y[1] G[5] Y[2] Y[2] R[0] Y[3] Y[3] R[1] Y[4] Y[4] R[2] Y[5] Y[5] R[3] Y[6] Y[6] R[4] Y[7] Y[7] Freescale Semiconductor 7 C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] ...
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... Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Active Line n+1th frame invalid ...
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... Applications Processors for Consumer Products, Rev Section 4.7.8.2.2, “Gated Clock n+1th frame 1st byte is that of a typical sensor. Some other sensors may have a slightly IP2 IP3 Figure 46. Sensor Interface Timing Diagram Figure 45). All incoming pixel clocks are invalid 1st byte 1/IP1 Freescale Semiconductor Mode,”) ...
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... Data and control holdup time 4.7.8.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Electrical Characteristics Symbol Min Fpck 0.01 ...
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... Groups should not be overlapped. DAT[3] b) The bit order is expressed in DAT[4] each of the bit groups, for example B[0] = least significant blue pixel DAT[5] bit DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] — — — — — — Freescale Semiconductor ...
Page 89
... This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor LCD 18-bit 24 Bit ...
Page 90
... When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX53xD Applications Processors for Consumer Products, Rev NOTE NOTE Freescale Semiconductor ...
Page 91
... VSYNC HSYNC LINE 1 HSYNC DRDY IPP_DISP_CLK IPP_DATA Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor LINE 2 LINE 3 LINE Electrical Characteristics LINE n-1 LINE n m– ...
Page 92
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY IP11 Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX53xD Applications Processors for Consumer Products, Rev IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 IP12 IP7 IP5 Dn D1 IP10 End of frame IP15 Freescale Semiconductor ...
Page 93
... IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Figure 48 Symbol Value 1 Tdicp ( ) Display interface clock. Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × ...
Page 94
... DI’s counter. DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the × bus, in DI_CLK 2 (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. for integer DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD DISP_CLK_PERIOD for fractional --------------------------------------------------- - DI_CLK_PERIOD Freescale Semiconductor Unit ...
Page 95
... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor ± Accuracy = T diclk 0.62ns ...
Page 96
... The active intervals—during which data is transferred—are marked by the HSYNC signal being high. i.MX53xD Applications Processors for Consumer Products, Rev × ⎛ 2 DISP_CLK_DOWN 1 × ---------------------------------------------------------- - Tdicd = -- - T diclk ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_CLK_UP 1 × ----------------------------------------------- - Tdicu = -- - T diclk ceil ⎝ DI_CLK_PERIOD 2 51. NOTE ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...
Page 97
... VSYNC 621 622 HSYNC DRDY VSYNC Even Field 308 309 HSYNC DRDY VSYNC Odd Field Figure 51. TV Encoder Interface Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Pixel Data Timing 524 525 Even Field 262 263 264 265 ...
Page 98
... Degrees — 75 — dB — 0.8 — ±Degrees — 1.5 — ±% — –70 — dB — –47 — dB — 0.5 — ±Degrees — 2.5 — ±% — 0.1 — ±% — 1.0 — ±% Freescale Semiconductor ...
Page 99
... A pause between two different display accesses can be guaranteed by programing suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control signal can be switched at any time during access size. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Conditions — 2 ...
Page 100
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 3 100 Burst access mode with sampling by CS signal Freescale Semiconductor ...
Page 101
... Burst access mode with sampling by WR/RD signals IPP_CS IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Electrical Characteristics 101 ...
Page 102
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 3 102 Burst access mode with sampling by CS signal Freescale Semiconductor ...
Page 103
... DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Burst access mode with sampling by ENABLE signal Electrical Characteristics 103 ...
Page 104
... Table 65 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register). i.MX53xD Applications Processors for Consumer Products, Rev. 3 104 waiting waiting Freescale Semiconductor ...
Page 105
... Data Write system cycle time IP29 RS start IP30 CS start IP31 CS hold IP32 RS hold IP35 Write start IP36 Controls hold time for write i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor IP36 IP34 D1 IP28d Symbol Value ACCESS_SIZE_# Tcycwd ACCESS_SIZE_# Tdcsrr UP# Tdcsc UP# ...
Page 106
... T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 1 Typ Max 2 Tdicpw+1.24 Tdicurs+1.24 Tdicucs+1. –Tdicucs Tdicdcs – Tdicucs+1. –Tdicurs Tdicdrs – Tdicurs+1.24 Tdicuw+1. –Tdicuw Tdicdw–Tdicuw+1.24 — Tdicpr – Tdicdr – 1.24 ⎞ ⎠ ⎞ ⎠ ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor Unit ...
Page 107
... Reset Time Low OW2 Presence Detect High OW3 Presence Detect Low OW4 Reset Time High (includes recovery time order not to mask signaling by other devices on the 1-Wire bus, t i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor × ⎛ 2 DISP_DOWN_# 1 × ------------------------------------------------- - = -- - T DI_CLK ceil ⎝ ...
Page 108
... OW6 OW5 Symbol t LOW0 t SLOT t REC Figure 61 depicts the Read Sequence timing, and OW8 OW8 OW11 OW9 OW10 Figure 61. Read Sequence Timing Diagram t REC Min Typ Max 60 100 120 OW5 117 120 1 — — Table 68 Freescale Semiconductor Unit µs µs µs ...
Page 109
... System CLK frequency 2a Clock high time 2b Clock low time 3a Clock fall time 3b Clock rise time 4a Output delay time 4b Output setup time PWMO = 30 pF i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 68. WR1 /RD Timing Parameters Symbol t LOW1 t SLOT LOWR t RDV t RELEASE Table 69 lists the PWM timing parameters ...
Page 110
... Applications Processors for Consumer Products, Rev. 3 110 SI2 Parameter 1 1 – where all signals have the same capacitive load value. SI1 Symbol Min Max S — 1.25 rise S — 1.25 fall C — 20 host Freescale Semiconductor Unit V/ns V/ns pF ...
Page 111
... Max difference in cable propagation delay without accounting for ground bounce 1 Values provided where applicable. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 71. PATA Timing Parameters Description UDMA2, UDMA3 UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Electrical Characteristics ...
Page 112
... Applications Processors for Consumer Products, Rev. 3 112 Table 72 lists the timing parameters for PIO read. Figure 64. PIO Read Timing Diagram Table 72. PIO Read Timing Parameters Value Controlling Variable time_1 time_2r time_9 time_2 (affects tsu and tco) — time_ax time_pio_rdx time_1, time_2r, time_9 Freescale Semiconductor ...
Page 113
... Avoid bus contention when switching buffer on by making ton long enough — — Avoid bus contention when switching buffer off by making toff long enough i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 73 lists the timing parameters for PIO write. Figure 65. Multi-word DMA (MDMA) Timing Table 73. PIO Write Timing Parameters ...
Page 114
... MDMA write, and Figure 66. MDMA Read Timing Diagram Figure 67. MDMA Write Timing Diagram Value × T – (tsu + tco + 2 Table 74 lists Controlling Variable time_m time_d time_k time_d, time_k time_d — time_d time_k × × tbuf + 2 tcable2) time_d, 2 time_k Freescale Semiconductor ...
Page 115
... UDMA in transfer starts, host terminates transfer, Figure 70 Table 75 lists the timing parameters for UDMA in burst. Figure 68. UDMA in Transfer Starts Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Value × T – tskew1 × T – tskew1 and Figure 67) equals (tk – ...
Page 116
... Applications Processors for Consumer Products, Rev. 3 116 Table 75. UDMA in Burst Timing Parameters Description × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) Controlling Variable time_ack time_env tskew3, ti_ds, ti_dh should be low enough Freescale Semiconductor ...
Page 117
... UDMA out transfer starts, host terminates transfer, Figure 73 Table 76 lists the timing parameters for UDMA out burst. Figure 71. UDMA Out Transfer Starts Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Description × T – (tskew1 + tskew2 + tskew6) × × × ...
Page 118
... Applications Processors for Consumer Products, Rev. 3 118 Value × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × T – (tskew1 + tskew2) × × Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc Freescale Semiconductor ...
Page 119
... Parameters Differential peak voltage (typically 0.71 V) Common mode voltage (refclk_p + refclk_m Total phase jitter Minimum/maximum duty cycle Frequency range i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Value × tsui + tco + tbuf + tbuf × T – (tskew1) × T – (tskew1 + tskew2) × ...
Page 120
... Table 78. SATA2 PHY Transmitter Characteristics Parameters Transmit common mode voltage Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) i.MX53xD Applications Processors for Consumer Products, Rev. 3 120 NOTE Symbol Min V 0.4 CTM — –0.5 Figure 74. The square Typ Max Unit — 0.6 V — 0.5 dB Freescale Semiconductor ...
Page 121
... The reference clock input frequency must fall within the specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the termination impedance is not of consequence. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol Min — ...
Page 122
... Applications Processors for Consumer Products, Rev. 3 122 Figure 76 depicts the SJC boundary scan timing. SJ1 SJ2 VM VIH VIL Figure 75. Test Clock Input Timing Diagram SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid Table 80. SJ2 VM SJ3 VIH SJ5 Freescale Semiconductor ...
Page 123
... Boundary scan input data hold time SJ6 TCK low to output data valid SJ7 TCK low to output high impedance SJ8 TMS, TDI data set-up time i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 78 ...
Page 124
... Max 25 — ns — — 100 — — ns Timing Parameter Range Units Min Max — 0.7 ns — 1.5 ns — 24.2 — 31.3 ns — 1.5 — 13.6 — 18.0 40.0 — ns 16.0 — ns 16.0 — ns 40.0 — ns 16.0 — ns 16.0 — ns Freescale Semiconductor ...
Page 125
... The SSI timing diagrams use generic signal names wherein the names used in the i.MX53 Reference Manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor srckp srckpl srckph V ...
Page 126
... Internal Clock Operation lists the timing parameters for the SS3 SS12 SS15 SS18 SS19 Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns Freescale Semiconductor ...
Page 127
... Transmit and Receive sections of the SSI. • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Parameter Synchronous Internal Clock Operation NOTE Electrical Characteristics ...
Page 128
... Parameter Internal Clock Operation lists the timing parameters for the SS3 SS13 SS21 SS49 Min Max 81.4 — 36.0 — — 6.0 36.0 — — 6.0 — 15.0 — 15.0 — 15.0 — 15.0 10.0 — 0.0 — Freescale Semiconductor Unit ...
Page 129
... The terms WL and BL refer to Word Length (WL) and Bit Length (BL). • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Parameter Oversampling Clock Operation NOTE Electrical Characteristics ...
Page 130
... External Clock Operation lists the timing parameters for SS24 SS33 SS39 SS38 SS45 SS46 Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns Freescale Semiconductor ...
Page 131
... The terms WL and BL refer to Word Length (WL) and Bit Length (BL). • For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Parameter Synchronous External Clock Operation NOTE Electrical Characteristics ...
Page 132
... SS25 SS28 SS30 SS32 SS35 SS40 Parameter External Clock Operation lists the timing parameters for the SS24 SS34 SS41 SS36 Min Max Unit 81.4 — — ns — 6 — ns — 6.0 ns –10 15 — ns –10 15 — ns — 6.0 ns — 6 — — ns Freescale Semiconductor ...
Page 133
... UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 88 lists the UART RS-232 serial mode transmit timing characteristics. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor NOTE Table 87 shows the UART I/O configuration based on the Table 87 ...
Page 134
... UA1 UA1 Min Max 1 – 1/F + baud_rate 2 T ref_clk ref_clk Table 89 Possible Parity Bit Next Start STOP Bit 7 Par Bit Bit BIT UA2 UA2 Min Max 2 – 1/F + baud_rate ) 1/(16*F ) baud_rate baud_rate Table 90 Freescale Semiconductor Units — lists Units — lists ...
Page 135
... The UART receiver can tolerate 1/(16*F exceed 3/(16*F ). baud_rate Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. baud_rate i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor UA3 Bit 1 Bit 2 Bit 3 Bit 4 Symbol t TIRbit t (3/16)*(1/F ...
Page 136
... Applications Processors for Consumer Products, Rev. 3 136 Parameters.” Direction Transmit enable, active low TX data when USB_TXOE_B is low Differential RX data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 RX indicator when USB_TXOE_B is high US1 US4 Signal Description US3 US2 Freescale Semiconductor ...
Page 137
... US2 TX Rise/Fall Time USB_SE0_VM US3 TX Rise/Fall Time USB_TXOE_B US4 TX Duty Cycle US7 RX Rise/Fall Time US8 RX Rise/Fall Time USB_SE0_VM i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor US7 Signal Name Direction Min USB_DAT_VP Out -— Out — Out — USB_DAT_VP Out 49 ...
Page 138
... Applications Processors for Consumer Products, Rev. 3 138 Direction Out Transmit enable, active low Out TX data when USB_TXOE_B is low Out SE0 drive when USB_TXOE_B is low In Buffered data on DP when USB_TXOE_B is high In Buffered data on DM when USB_TXOE_B is high US9 US12 Signal Description US11 US10 Freescale Semiconductor ...
Page 139
... USB_DAT_VP US10 TX Rise/Fall Time USB_SE0_VM US11 TX Rise/Fall Time USB_TXOE_B US12 TX Duty Cycle USB_DAT_VP US15 RX Rise/Fall Time US16 RX Rise/Fall Time i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor US15 Signal Min Source Out — Out — Out — Out 49.0 USB_VP1 In — ...
Page 140
... Applications Processors for Consumer Products, Rev. 3 140 Direction Out Transmit enable, active low Out (Tx data when USB_TXOE_B is low In (Rx data when USB_TXOE_B is high Out (Tx data when USB_TXOE_B low In (Rx data when USB_TXOE_B high US18 US22 US26 US28 Signal Description US20 US19 US22 US27 Freescale Semiconductor ...
Page 141
... US19 TX Rise/Fall Time US20 TX Rise/Fall Time US21 TX Duty Cycle US22 TX Overlap US26 RX Rise/Fall Time US27 RX Rise/Fall Time US28 RX Skew i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Signal Name Direction Min USB_DAT_V Out — P USB_SE0_V Out — M USB_TXOE Out — ...
Page 142
... Applications Processors for Consumer Products, Rev. 3 142 Direction Out Transmit enable, active low Out TX VP data when USB_TXOE_B is low Out TX VM data when USB_TXOE_B is low data when USB_TXOE_B is high data when USB_TXOE_B is high US30 US34 Signal Description US32 US31 Freescale Semiconductor ...
Page 143
... US31 TX Rise/Fall Time US32 TX Rise/Fall Time US33 TX Duty Cycle US34 TX Overlap US38 RX Rise/Fall Time US39 RX Rise/Fall Time US40 RX Skew i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor US38 US40 US39 Signal Direction Min USB_DAT_VP Out — USB_SE0_V Out — M USB_TXOE_ Out — ...
Page 144
... Stop. The link asserts this signal for 1 clock cycle to stop the Out data stream currently on the bus. In Next. The PHY asserts this signal to throttle the data. US16 US16 US17 Parameter Signal Description US17 Conditions / Min Max Unit Reference Signal 6.0 — 0.0 — — 9 Freescale Semiconductor ...
Page 145
... Reference Clock frequency 24 MHz Rise/fall time — Jitter (peak-peak) < 1.2 MHz Jitter (peak-peak) > 1.2 MHz Duty-cycle Reference Clock frequency 24 MHz i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 102. USB PHY AC Timing Parameters Min Typ 75 — 4 0.5 75 — 4 0.5 — ...
Page 146
... Comparators Thresholds Conditions Min — 0.8 — 0.8 — 0.2 — 4.4 Ω ±10% (steady state). No external resistors required. Typ 24 Typ 1 -- 32.768/32.0 Typ Max Unit 1.4 2.0 V 1.4 4.0 V 0.45 0.8 V 4.6 4.75 V Max Units 27 MHz Max Units -- kHz Freescale Semiconductor ...
Page 147
... Fuse Map document and Boot chapter in i.MX53 Reference Manual. Table 109. Fuses and Associated Pins Used for Boot Direction at Pin Reset BOOT_MODE[1] Input BOOT_MODE[0] Input i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol Min V 1.15 VID_DIG_PLL V 1.7 VDD_ANA_PLL — ...
Page 148
... BT_FUSE_SEL = ‘0’. Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses. Comment Only SS1 is supported Only SS1 is supported Only SS1 is supported Freescale Semiconductor ...
Page 149
... By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to achieve the standard operating mode (see VDD_DIG_PLL on should be configured by software by boot code after power-up to 1.3 V output. This is done by programming the PLL1P2_VREG bits. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Allocated Pads During Boot Table Boot Mode Configuration Comment • ...
Page 150
... Applications Processors for Consumer Products, Rev. 3 150 Figure 99 Figure 100 Figure 98 Package Top View shows the bottom view and the ball shows the side view of the 19×19 Freescale Semiconductor ...
Page 151
... Figure 99 Package, 529 Solder Balls, Bottom View i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Figure 100 Package Side View Package Information and Contact Assignments 151 ...
Page 152
... F11 NVCC_GPIO F8 NVCC_JTAG G9 NVCC_KEYPAD F7 NVCC_LCD J6, J7 NVCC_LVDS U13 NVCC_LVDS_BG U14 NVCC_NANDF T12 NVCC_PATA N7 NVCC_RESET H16 NVCC_SD1 H15 i.MX53xD Applications Processors for Consumer Products, Rev. 3 152 98, Figure 99, and Figure 100. Table 113 shows the package ball map. Package Contact Assignment(s) Freescale Semiconductor ...
Page 153
... A15, B15 VPH A9, B9 Table 112 displays an alpha-sorted list of the signal assignments including power rails. The table also includes out of reset pad state. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Package Contact Assignment(s) 153 ...
Page 154
... Input 360 KΩ PD Input 360 KΩ PD Input 360 KΩ PD Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 155
... NVCC_LCD DISP0_DAT5 H3 NVCC_LCD DISP0_DAT6 G1 NVCC_LCD DISP0_DAT7 H6 NVCC_LCD DISP0_DAT8 G6 NVCC_LCD i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode GPIO ALT1 GPIO-4 gpio4_GPIO[16] GPIO ALT1 GPIO-4 gpio4_GPIO[17] ...
Page 156
... Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Output Low Input — Output High Output High Output High Freescale Semiconductor ...
Page 157
... U22 NVCC_EMI_DRAM DRAM_D23 R23 NVCC_EMI_DRAM DRAM_D24 Y20 NVCC_EMI_DRAM DRAM_D25 W21 NVCC_EMI_DRAM i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode DDR3 ALT0 EXTMC emi_DRAM_D[0] DDR3 ALT0 ...
Page 158
... High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output Low Output Low Output Low Output Low Output High Output Low Output Low Output Low Freescale Semiconductor ...
Page 159
... DRAM_SDQS Y22 NVCC_EMI_DRAM 3 DRAM_SDQS Y23 NVCC_EMI_DRAM 3_B DRAM_SDWE L19 NVCC_EMI_DRAM i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode DDR3 ALT0 EXTMC emi_DRAM_SDB A[2] DDR3 ...
Page 160
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 161
... AC5 NVCC_EIM_MAIN EIM_DA8 AA8 NVCC_EIM_MAIN EIM_DA9 W10 NVCC_EIM_MAIN EIM_EB0 AC3 NVCC_EIM_MAIN i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-3 gpio3_GPIO[30] UHVIO ALT1 ...
Page 162
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 163
... NVCC_KEYPAD KEY_COL4 E5 NVCC_KEYPAD KEY_ROW0 B3 NVCC_KEYPAD KEY_ROW1 D6 NVCC_KEYPAD KEY_ROW2 D5 NVCC_KEYPAD i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode GPIO ALT0 GPIO-4 gpio4_GPIO[3] GPIO ALT0 GPIO-4 gpio4_GPIO[4] ...
Page 164
... KΩ PD — — Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Freescale Semiconductor ...
Page 165
... NVCC_PATA PATA_DATA11 M6 NVCC_PATA PATA_DATA12 N5 NVCC_PATA PATA_DATA13 N6 NVCC_PATA PATA_DATA14 P6 NVCC_PATA PATA_DATA15 P5 NVCC_PATA i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode LVDS ALT0 GPIO-6 gpio6_GPI[23] LVDS ALT0 ...
Page 166
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Output — Output — Input 100 KΩ PU Input 100 KΩ PU — — — — — — — — — — — — — — Freescale Semiconductor ...
Page 167
... B TVDAC_IOR AC21 TVDAC_AHVDDRG B TVDAC_VREF Y18 TVDAC_AHVDDRG B USB_H1_DN B17 USB_H1_VDDA25, USB_H1_VDDA33 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-1 gpio1_GPIO[20] UHVIO ALT1 GPIO-1 gpio1_GPIO[18] ...
Page 168
... ANALOG — XTALO XTAL SC Section 5.1, “Boot Mode Configuration Pins” NOTE 1 Config./ Direction Value — — — — — — — — — — — — — — — — — — — — — — for details. Freescale Semiconductor ...
Page 169
... Pitch Ball Map shows the 19 × 19 mm, 0.8 pitch ball map. Table 113 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Table 113 mm, 0.8 Pitch Ball Map 169 ...
Page 170
... Package Information and Contact Assignments i.MX53xD Applications Processors for Consumer Products, Rev. 3 170 Table 113 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
Page 171
... Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Table 113 mm, 0.8 Pitch Ball Map 171 ...
Page 172
... Package Information and Contact Assignments i.MX53xD Applications Processors for Consumer Products, Rev. 3 172 Table 113 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
Page 173
... This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid location) for the mm, 0.4 mm pitch PoP package. 6.3.1 Case PoP, 0.4 mm Pitch Ball Matrix i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Figure 101. 12x12 mm PoP Top View 173 ...
Page 174
... Package Information and Contact Assignments i.MX53xD Applications Processors for Consumer Products, Rev. 3 174 Figure 102 PoP, Bottom View Freescale Semiconductor ...
Page 175
... Table 118 displays an alpha-sorted list of the signal assignments including associated power supplies. The table also includes out of reset pad state. i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Figure 103 PoP, Side View 101, Figure ...
Page 176
... F19 NVCC_LVDS_BG F18 NVCC_NANDF G12 NVCC_PATA N6 NVCC_RESET AD18 NVCC_SD1 AC20 NVCC_SD2 AC16 NVCC_SRTC_POW F13 NVCC_XTAL F14 POP_VACC AG14 POP_VCCMM C8, L3 POP_VCCQMM C11 POP_VCCQMM1 H3 POP_VDD1 C3, C13, C26, T3, T27, AG6, AG26 i.MX53xD Applications Processors for Consumer Products, Rev. 3 176 Contact Assignment Freescale Semiconductor ...
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... Table 115 PoP Top Ground, Power, Sense, and Reference Contact Assignments Contact Name DDR_VREF GND POP_VACC i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Contact Assignment Contact Assignment P2, M22 A12, A15, A18, A21, B5, B8, B10, C1, C23, F2, F23, J2, J23, M2, M23, P23, ...
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... PATA_DATA3 PATA_DATA8 PATA_DATA8 PATA_DATA9 PATA_DATA9 PATA_DATA10 PATA_DATA10 PATA_DATA11 PATA_DATA11 Table 116. With NAND flash selected Required for Required for 16-bit 8-bit NAND NAND Flash? Flash? Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes No Yes No Yes No Yes Freescale Semiconductor ...
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... CSI0_DAT11 R7 — CSI0_DAT12 U1 — CSI0_DAT13 R1 — CSI0_DAT14 T1 — CSI0_DAT15 P1 — i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Associated Top Ball PATA_DA0 PATA_IORDY PATA_RESETB I/O Buffer Power Rail Type Mode NVCC_RESET LVIO ALT0 NVCC_RESET LVIO ALT0 NVCC_CKIH ANALOG ALT0 ...
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... Input gpio5_GPIO[7] Input gpio5_GPIO[8] Input gpio5_GPIO[9] Input gpio5_GPIO[10] Input gpio5_GPIO[11] Input gpio5_GPIO[12] Input Freescale Semiconductor Config./ Value 360 KΩ PD 360 KΩ PD 360 KΩ PD 360 KΩ PD 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ ...
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... AA24 AB9 DRAM_A5 M23 W1 DRAM_A6 P23 V2 DRAM_A7 N23 U1 DRAM_A8 M24 T2 DRAM_A9 T23 T1 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ...
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... Output High emi_DRAM_D[21] Output High emi_DRAM_D[22] Output High emi_DRAM_D[23] Output High emi_DRAM_D[24] Output High emi_DRAM_D[25] Output High emi_DRAM_D[26] Output High emi_DRAM_D[27] Output High emi_DRAM_D[28] Output High emi_DRAM_D[29] Output High emi_DRAM_D[3] Output High emi_DRAM_D[30] Output High Freescale Semiconductor Config./ Value — ...
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... DRAM_SDCKE1 F22 AC4 DRAM_SDCLK_ — 0 DRAM_SDCLK_ — 0_B DRAM_SDCLK_ H23 Y2 1 DRAM_SDCLK_ J23 Y1 1_B i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM DDR3 ALT0 ...
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... Input B[3] emi_DRAM_SDWE Output High ECKIL — emi_EIM_A[16] Output 2 emi_EIM_A[17] Output 2 emi_EIM_A[18] Output 2 emi_EIM_A[19] Output 2 emi_EIM_A[20] Output 2 emi_EIM_A[21] Output 2 emi_EIM_A[22] Output 2 Freescale Semiconductor Config./ Value Low High Low High Low High Low High — — — — — — — — ...
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... F7 — EIM_DA0 K1 — EIM_DA1 G11 — EIM_DA10 L7 — EIM_DA11 K7 — EIM_DA12 E2 D1 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ...
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... Output 2 emi_EIM_OE Output — emi_EIM_RW Output — emi_EIM_WAIT Output — EXTAL — FASTR_ANA — Freescale Semiconductor Config./ Value 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU — ...
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... GPIO_2 AG11 — GPIO_3 AC12 — GPIO_4 AH11 — GPIO_5 AJ11 — GPIO_6 AJ12 — i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_CKIH ANALOG — NVCC_FEC UHVIO ALT1 NVCC_FEC UHVIO ALT1 NVCC_FEC UHVIO ...
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... Input gpio7_GPI[30] Input gpio7_GPI[29] Input gpio7_GPI[28] Input gpio7_GPI[27] Input gpio7_GPI[26] Input gpio7_GPI[23] Input gpio7_GPI[22] Input Freescale Semiconductor Config./ Value 360 KΩ PD 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ KΩ PU Keeper 47 KΩ KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ ...
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... N2 L1 PATA_DA_1 AB2 — PATA_DA_2 Y3 — PATA_DATA0 B9 A7 PATA_DATA1 B8 B6 PATA_DATA10 B10 A8 i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ...
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... Output — _REQ src_POR_B Input src_RESET_B Input SATA_REFCLKM — SATA_REFCLKP — SATA_REXT — SATA_RXM — Freescale Semiconductor Config./ Value 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ ...
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... TVDAC_COMP A25 — TVDAC_IOB A23 — TVDAC_IOG B24 — TVDAC_IOR C29 — USB_H1_DN AH21 — i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor I/O Buffer Power Rail Type Mode VPH ANALOG — VPH ANALOG — VPH ANALOG — NVCC_SD1 UHVIO ...
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... Function ion USB_H1_DP — USB_H1_GPANAIO — USB_H1_RREFEX — T USB_H1_VBUS — USB_OTG_DN — USB_OTG_DP — USB_OTG_GPANAI — O USB_OTG_ID — USB_OTG_RREFE — XT USB_OTG_VBUS — XTAL — Freescale Semiconductor Config./ Value — — — — — — — — — — — Section 5.1, ...
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... Table 119. PoP 12 × 12 mm, 0.4 Pitch Top Ball Map i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 193 ...
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... Package Information and Contact Assignments Table 119. PoP 12 × 12 mm, 0.4 Pitch Top Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 3 194 Freescale Semiconductor ...
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... Table 119. PoP 12 × 12 mm, 0.4 Pitch Top Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 195 ...
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... Package Information and Contact Assignments Table 120. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map i.MX53xD Applications Processors for Consumer Products, Rev. 3 196 Freescale Semiconductor ...
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... Table 120. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 197 ...
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... Package Information and Contact Assignments Table 120. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 3 198 Freescale Semiconductor ...
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... Table 120. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 199 ...
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... Package Information and Contact Assignments Table 120. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 3 200 Freescale Semiconductor ...