CS8405A-CS Cirrus Logic Inc, CS8405A-CS Datasheet - Page 12

• Manufacturer Part Number: CS8405A-CS
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8405A-CS

• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Transceiver Type: Digital Audio
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5. AES3 TRANSMITTER
The CS8405A includes an AES3 digital audio
transmitter. A comprehensive buffering scheme
provides write access to the channel status and user
data. This buffering scheme is described in “Ap-
pendix B: Channel Status and User Data Buffer
Management” on page 34.
The AES3 transmitter encodes and transmits audio
and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
Audio and control data are multiplexed together
and bi-phase mark encoded. The resulting bit
stream is driven to an output connector either di-
rectly or through a transformer. The transmitter is
clocked from the clock input pin, OMCK. If
OMCK is asynchronous to the data source, an in-
terrupt bit(TSLIP) is provided that will go high ev-
ery time a data sample is dropped or repeated. Be
aware that the pattern of slips does not have hyster-
esis and so the occurrence of the interrupt condition
is not deterministic.
The channel status (C) and user (U) bits in the
transmitted data stream are taken from storage ar-
eas within the CS8405A. The user can manually
access the internal storage or configure the
CS8405A to run in one of several automatic modes.
“Appendix B: Channel Status and User Data Buffer
Management” on page 34 provides detailed de-
scriptions of each automatic mode and describes
methods of manually accessing the storage areas.
The transmitted user bit data can optionally be in-
put through the U pin, under the control of a control
port register bit. Figure 7 shows the timing require-
ments for inputting U data through the U pin.
5.1
The TCBL pin is used to control or indicate the
start of transmitted channel status block boundaries
and may be an input or an output.
12
Transmitted Frame and Channel
Status Boundary Timing
In some applications, it may be necessary to control
the precise timing of the transmitted AES3 frame
boundaries. This may be achieved in two ways:
a) With TCBL set to input, driving TCBL high for
>3 OMCK clocks will cause a frame start, as well
as a new channel status block start.
b) If the serial audio input port is in slave mode and
TCBL is set to output, the start of the A channel
sub-frame will be aligned with the leading edge of
ILRCK.
5.2
The line drivers are low skew, low impedance, dif-
ferential outputs capable of driving cables directly.
Both drivers are set to ground during reset (RST =
low), when no AES3 transmit clock is provided,
and optionally under the control of a register bit.
The CS8405A also allows immediate muting of the
AES3 transmitter audio data through a control reg-
ister bit.
External components are used to terminate and iso-
late the external cable from the CS8405A. These
components are detailed in “Appendix A: External
AES3/SPDIF/IEC60958
nents” on page 33.
5.3
An AES3 stream may be used in more than one
way to transmit 96 kHz sample rate data. One
method is to double the frame rate of the current
format. This results in a stereo signal with a sample
rate of 96 kHz, carried over a single twisted pair ca-
ble. An alternate method is implemented using the
two sub-frames in a 48 kHz frame rate AES3 signal
to carry consecutive samples of a mono signal, re-
sulting in a 96 kHz sample rate stream. This allows
older equipment, whose AES3 transmitters and re-
ceivers are not rated for 96 kHz frame rate opera-
tion, to handle 96 kHz sample rate information. In
this “mono mode”, two AES3 cables are needed for
stereo data transfer. The CS8405A offers mono
TXN and TXP Drivers
Mono Mode Operation
Transmitter
CS8405A
DS469PP4
Compo-