PIC16LC774-I/PQ Microchip Technology, PIC16LC774-I/PQ Datasheet - Page 133

• Manufacturer Part Number: PIC16LC774-I/PQ
• Description: 44 PIN, 7KB OTP, 256 RAM, 33 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774-I/PQ

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.8
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked by the POR pulse. When the
PWRT delay expires the Oscillator Start-up Timer is
activated. The total time-out will vary based on oscilla-
tor configuration and the status of the PWRT. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
9
power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure
synchronize more than one PICmicro microcontroller
operating in parallel.
TABLE 12-3
TABLE 12-4
TABLE 12-5
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1:
Oscillator Configuration
POR
1999 Microchip Technology Inc.
and
0
0
0
1
1
1
1
1
12-9). This is useful for testing purposes or to
Figure 12-10
XT, HS, LP
Time-out Sequence
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
BOR
RC
1
x
x
0
1
1
1
1
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
Figure
TO
1
0
x
1
0
0
u
1
Condition
depict time-out sequences on
12-7,
PD
1
x
0
1
1
0
u
0
72 ms + 1024T
Figure
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
PWRTE = 0
72 ms
12-8,
Advance Information
Figure 12-
Power-up
OSC
PWRTE = 1
1024T
Program
PC + 1
Counter
PC + 1
000h
000h
000h
000h
000h
—
OSC
Table 12-5
function registers, while
conditions for all the registers.
12.9
The Power Control/Status Register, PCON has two sta-
tus bits that provide indication of which power-up type
reset occurred.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is set
on a Power-on Reset. It must then be set by the user
and checked on subsequent resets to see if bit BOR
cleared, indicating a BOR occurred. However, if the
brown-out circuitry is disabled, the BOR bit is a "Don’t
Care" bit and is considered unknown upon a POR.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
(1)
Power Control/Status Register
(PCON)
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
72 ms + 1024T
shows the reset conditions for some special
Register
STATUS
Brown-out
72 ms
OSC
PIC16C77X
Table 12-6
---- --01
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
DS30275A-page 133
Register
Wake-up from
PCON
shows the reset
1024T
SLEEP
—
OSC