PIC16LC774-I/PQ Microchip Technology, PIC16LC774-I/PQ Datasheet - Page 64

• Manufacturer Part Number: PIC16LC774-I/PQ
• Description: 44 PIN, 7KB OTP, 256 RAM, 33 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16LC774-I/PQ

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-MQFP, 44-PQFP
• Processor Series: PIC16LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SPI, SSP, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16C77X
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address if the next byte is the comple-
tion of 10-bit address, and if this will be a read or write
data transfer.
SSPBUF is the register to which the transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
8.2.1
In slave mode, the SCL and SDA pins must be config-
ured as inputs. The MSSP module will override the
input state with the output data when required (slave-
transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
a)
b)
If the BF bit is set, the SSPSR register value is not
loaded into the SSPBUF, but bit SSPIF and SSPOV are
set.
fer byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low time for proper operation. The high and low times
of the I
MSSP module is shown in timing
parameter #101
DS30275A-page 64
Table 8-2
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
2
C specification as well as the requirement of the
SLAVE MODE
shows what happens when a data trans-
of the Electrical Specifications.
parameter #100
Advance Information
and
8.2.1.1
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for a 10-bit
address is as follows, with steps 7- 9 for slave-transmit-
ter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Note:
The SSPSR register value is loaded into the
SSPBUF register on the falling edge of the 8th
SCL pulse.
The buffer full bit, BF is set on the falling edge of
the 8th SCL pulse.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the 9th SCL pulse.
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address. This will clear bit UA and
release the SCL line.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
ADDRESSING
Following the Repeated Start condition
(step 7) in 10-bit mode, the user only
needs to match the first 7-bit address. The
user does not update the SSPADD for the
second half of the address.
1999 Microchip Technology Inc.