PIC17C42A-16/L Microchip Technology, PIC17C42A-16/L Datasheet - Page 120

• Manufacturer Part Number: PIC17C42A-16/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C42A-16/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: OTP
• Ram Size: 232 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 232 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC17C42A-16/LR; PIC17C42A-16/LR

PIC17C4X
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
DS30412C-page 120
Before Instruction
After Instruction
Forced NOP
Decode
PC
W
If REG
PC
If REG
PC
Q1
Q1
register 'f'
Compare f with WREG,
skip if f < WREG
[ label ] CPFSLT
0
(f) – WREG),
skip if (f) < (WREG)
(unsigned comparison)
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' < the contents of
WREG, then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
1
1 (2)
HERE
NLESS
LESS
None
Read
NOP
0011
Q2
Q2
=
=
<
=
f
=
255
Address (HERE)
?
WREG;
Address (LESS)
WREG;
Address (NLESS)
CPFSLT REG
:
:
0000
Execute
Execute
Q3
Q3
ffff
f
NOP
NOP
Q4
Q4
ffff
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example 2:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
REG1
C
DC
WREG
REG1
C
DC
WREG
REG1
C
DC
WREG
REG1
C
DC
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register 'f'
Decimal Adjust WREG Register
[ label ] DAW
0
s
If [WREG<3:0> >9] .OR. [DC = 1] then
else
If [WREG<7:4> >9] .OR. [C = 1] then
else
C
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0:
s = 1:
1
1
DAW
Read
0010
Q2
WREG<3:0> + 6
WREG<3:0>
WREG<7:4> + 6
WREG<7:4>
0xA5
??
0
0
0x05
0x05
1
0
0xCE
??
0
0
0x24
0x24
1
0
f
[0,1]
1996 Microchip Technology Inc.
255
REG1, 0
Result is placed in Data
memory location 'f' and
Result is placed in Data
memory location 'f'.
WREG.
111s
Execute
Q3
f,s
f<3:0>, s<3:0>;
f<7:4>, s<7:4>
ffff
f<3:0>, s<3:0>;
f<7:4>, s<7:4>
register 'f'
and other
specified
register
Write
Q4
ffff