PIC17C42A-16/L Microchip Technology, PIC17C42A-16/L Datasheet - Page 46

• Manufacturer Part Number: PIC17C42A-16/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C42A-16/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: OTP
• Ram Size: 232 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 232 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164317 - MODULE SKT MPLAB PM3 44PLCCDVA17XL441 - DEVICE ADAPTER FOR PIC17C42A309-1007 - ADAPTER 44-PLCC ZIF TO 40-DIPAC174002 - MODULE SKT PROMATEII 44PLCC
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC17C42A-16/LR; PIC17C42A-16/LR

PIC17C4X
7.2
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
FIGURE 7-5:
DS30412C-page 46
Note:
Note:
Table Writes to External Memory
If external write GLINTD = '1', Enable bit = '1', '1'
If an interrupt is pending or occurs during
the TABLWT , the two cycle table write
completes. The RA0/INT, TMR0, or T0CKI
interrupt flag is automatically cleared or
the
acknowledged.
AD15:AD0
pending
Instruction
executed
TABLWT WRITE TIMING (EXTERNAL MEMORY)
Instruction
fetched
ALE
WR
OE
peripheral
Q1 Q2 Q3 Q4
'1'
INST (PC-1)
TABLWT
PC
interrupt
Q1 Q2 Q3 Q4
TABLWT cycle1
is
INST (PC+1)
PC+1
Flag bit, Do table write. The highest pending interrupt is cleared.
7.2.2
The “i” operand of the TABLWT instruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically
Example 7-1, the TBLPTR register is not automatically
incremented.
EXAMPLE 7-1:
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
MOVLW
TABLWT
Q1 Q2 Q3 Q4
Data write cycle
TABLWT cycle2
TBL
TABLE WRITE CODE
incremented
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
LOW (DATA)
0,0,WREG
Data out
TABLE WRITE
Q1 Q2 Q3 Q4
INST (PC+2)
INST (PC+1)
1996 Microchip Technology Inc.
PC+2
for
; Clear WDT
;
;
;
; Load HI byte
;
; Load LO byte
;
;
;
;
the
address
in TABLATCH
in TABLATCH
and write to
program memory
(Ext. SRAM)
next
write.
In