PIC18C601-I/L Microchip Technology, PIC18C601-I/L Datasheet - Page 247

• Manufacturer Part Number: PIC18C601-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,68PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C601-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCCXLT68L1 - SOCKET TRANSITION ICE 68PLCCAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C601I/L

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2001 Microchip Technology Inc.
After Call
Before Instruction
After Instruction
operation
Decode
No
PC
WRG
STATUS =
BSR
WREG
STATUS =
BSR
PC
Q1
=
=
=
=
=
=
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ’s’ = 1, the contents of
the shadow registers WS, STA-
TUSS and BSRS are loaded into
their corresponding registers,
WREG, STATUS and BSR. If
’s’ = 0, no update of these
registers occurs (default).
1
2
RETURN
RETURN FAST
0000
No
No
Q2
TOS
04h
00h
00h
04h
00h
00h
TOS
[0,1]
W,
PC,
RETURN [s]
0000
BSR,
operation
Process
Data
No
STATUS,
Q3
0001
from stack
Advance Information
operation
Pop PC
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
C
N
Z
REG
WREG
C
N
Z
Q1
PIC18C601/801
=
=
=
=
=
=
=
=
=
register ’f’
Rotate Left f through Carry
[ label ] RLCF
0
d
a
(f<n>)
(f<7>)
(C)
C,N,Z
The contents of register 'f' are
rotated one bit to the left through the
Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result
is stored back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
1
1
RLCF
Read
Q2
0011
1110 0110
0
?
?
1110 0110
1100 1100
1
1
0
f
[0,1]
[0,1]
C
dest<0>
255
dest<n+1>,
C,
01da
Process
REG, W
Data
Q3
register f
DS39541A-page 247
f [,d [,a]]
ffff
destination
Write to
Q4
ffff