PIC18F4685-E/PT Microchip Technology, PIC18F4685-E/PT Datasheet - Page 203
![96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4685-E/PT
Manufacturer Part Number
PIC18F4685-E/PT
Description
96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F4685-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
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Manufacturer:
MICROCHIP
Quantity:
2 000
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Part Number:
PIC18F4685-E/PT
Manufacturer:
Microchip Technology
Quantity:
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Manufacturer:
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Quantity:
20 000
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 203 of 484
- Download datasheet (9Mb)
17.4.3.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit, SSPIF (PIR1<3>), must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
If SEN is enabled (SSPCON2<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit
CKP (SSPCON<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
© 2009 Microchip Technology Inc.
Reception
PIC18F2682/2685/4682/4685
17.4.3.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low regardless of SEN (see Section 17.4.4 “Clock
Stretching” for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit, CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
Transmission
DS39761C-page 203
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