PIC18F4685-E/PT Microchip Technology, PIC18F4685-E/PT Datasheet - Page 340
![96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4685-E/PT
Manufacturer Part Number
PIC18F4685-E/PT
Description
96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F4685-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4685-E/PT
Manufacturer:
MICROCHIP
Quantity:
2 000
Company:
Part Number:
PIC18F4685-E/PT
Manufacturer:
Microchip Technology
Quantity:
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- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 340 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
FIGURE 23-7:
23.11 Programming Time Segments
Some requirements for programming of the time
segments:
• Prop_Seg + Phase_Seg 1 ≥ Phase_Seg 2
• Phase_Seg 2 ≥ Sync Jump Width.
For example, assume that a 125 kHz CAN baud rate is
desired, using 20 MHz for F
a baud rate prescaler value of 04h gives a T
To obtain a Nominal Bit Rate of 125 kHz, the Nominal
Bit Time must be 8 μs or 16 T
Using 1 T
and 7 T
point at 10 T
Phase Segment 2.
By the rules above, the Sync Jump Width could be the
maximum of 4 T
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. Typically, an SJW of 1 is enough.
23.12 Oscillator Tolerance
As a rule of thumb, the bit timing requirements allow
ceramic resonators to be used in applications with
transmission rates of up to 125 Kbit/sec. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
DS39761C-page 340
T
Q
Q
for Phase Segment 1 would place the sample
Q
for the Sync_Seg, 2 T
Q
Sync
after the transition. This leaves 6 T
Q
. However, normally a large SJW is
SHORTENING A BIT PERIOD (SUBTRACTING SJW FROM PHASE SEGMENT 2)
Segment
Prop
OSC
Q
.
. With a T
Q
for the Prop_Seg
OSC
Actual Bit Length
Q
of 500 ns.
of 50 ns,
Segment 1
Phase
Q
for
Nominal Bit Length
Sample Point
23.13 Bit Timing Configuration
The
BRGCON2, BRGCON3) control the bit timing for the
CAN bus interface. These registers can only be
modified
devices are in Configuration mode.
23.13.1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of T
23.13.2
The PRSEG bits set the length of the propagation seg-
ment in terms of T
Phase Segment 1 in T
many times the RXCAN pin is sampled. Setting this bit
to a
at T
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘0’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘0’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
Information Processing Time (which is fixed at 2 T
the PIC18F2682/2685/4682/4685).
23.13.3
The PHSEG2<2:0> bits set the length (in T
Segment 2 if the SEG2PHTS bit is set to a ‘1’. If the
SEG2PHTS bit is set to a ‘0’, then the PHSEG2<2:0>
bits have no effect.
Q
‘
1
/2 before the sample point and once at the normal
’
Baud Rate Control registers
causes the bus to be sampled three times: twice
Registers
‘
1
when
’
, then the length of Phase Segment 2 is
BRGCON1
BRGCON2
BRGCON3
Segment 2
Phase
Q
the
. The SEG1PH bits set the length of
Q
.
© 2009 Microchip Technology Inc.
Q
PIC18F2682/2685/4682/4685
. The SAM bit controls how
≤ SJW
(BRGCON1,
Q
) of Phase
Q
for
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