PIC18F4685-E/PT Microchip Technology, PIC18F4685-E/PT Datasheet - Page 31
![96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4685-E/PT
Manufacturer Part Number
PIC18F4685-E/PT
Description
96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F4685-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Price
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Manufacturer:
MICROCHIP
Quantity:
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PIC18F4685-E/PT
Manufacturer:
Microchip Technology
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- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 31 of 484
- Download datasheet (9Mb)
2.7.1
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in full
power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC3:FOSC0 Configu-
ration bits), the secondary clock (Timer1 oscillator) and
the internal oscillator block. The clock source changes
immediately after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The
IRCF2:IRCF0, select the frequency output of the
internal oscillator block to drive the device clock. The
choices are the INTRC source, the INTOSC source
(8 MHz) or one of the frequencies derived from the
INTOSC postscaler (31 kHz to 4 MHz). If the internal
oscillator block is supplying the device clock, changing
the states of these bits will have an immediate change
on the internal oscillator’s output. On device Resets,
the default output frequency of the internal oscillator
block is set at 1 MHz.
When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which
internal oscillator acts as the source. This is done with
the
(OSCTUNE<7>). Setting this bit selects INTOSC as a
31.25 kHz clock source by enabling the divide-by-256
output of the INTOSC postscaler. Clearing INTSRC
selects INTRC (nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the device clock. The
OSTS bit indicates that the Oscillator Start-up Timer
has timed out and the primary clock is providing the
device clock in primary clock modes. The IOFS bit
indicates when the internal oscillator block has
stabilized and is providing the device clock in RC Clock
modes. The T1RUN bit (T1CON<6>) indicates when
the Timer1 oscillator is providing the device clock in
secondary clock modes. In power-managed modes,
only one of these three bits will be set at any time. If
none of these bits are set, the INTRC is providing the
clock or the internal oscillator block has just started and
is not yet stable.
© 2009 Microchip Technology Inc.
INTSRC
Internal
OSCILLATOR CONTROL REGISTER
Oscillator
bit
in
the
Frequency
OSCTUNE
Select
PIC18F2682/2685/4682/4685
register
bits,
The IDLEN bit determines if the device goes into Sleep
mode or one of the Idle modes when the SLEEP
instruction is executed.
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 3.0
“Power-Managed Modes”.
2.7.2
PIC18F2682/2685/4682/4685 devices contain circuitry
to prevent clock “glitches” when switching between
clock sources. A short pause in the device clock occurs
during the clock switch. The length of this pause is the
sum of two cycles of the old clock source and three to
four cycles of the new clock source. This formula
assumes that the new clock source is stable.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power-Managed Modes”.
Note 1: The Timer1 oscillator must be enabled to
2: It is recommended that the Timer1
OSCILLATOR TRANSITIONS
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control regis-
ter (T1CON<3>). If the Timer1 oscillator is
not enabled, then any attempt to select a
secondary clock source when executing a
SLEEP instruction will be ignored.
oscillator be operating and stable before
executing the SLEEP instruction, or a very
long delay may occur while the Timer1
oscillator starts.
DS39761C-page 31
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