PIC18F4685-E/PT Microchip Technology, PIC18F4685-E/PT Datasheet - Page 373
![96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4685-E/PT
Manufacturer Part Number
PIC18F4685-E/PT
Description
96KB, Flash, 3328bytes-RAM, 36I/O, 8-bit Family,nanoWatt,ECAN 44 TQFP 10x10x1mm
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F4685-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4680 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4685-E/PT
Manufacturer:
MICROCHIP
Quantity:
2 000
Company:
Part Number:
PIC18F4685-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4685-E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 373 of 484
- Download datasheet (9Mb)
ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
=
=
=
=
register ‘f’
AND W with f
ANDWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) .AND. (f) → dest
N, Z
The contents of W are ANDed with
register ‘f’. If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ANDWF
Read
0001
Q2
17h
C2h
02h
C2h
f {,d {,a}}
01da
REG, 0, 0
Process
Data
Q3
ffff
destination
Write to
PIC18F2682/2685/4682/4685
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
BC
-128 ≤ n ≤ 127
if Carry bit is ‘1’
(PC) + 2 + 2n → PC
None
If the Carry bit is ‘1’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (HERE + 12)
0;
address (HERE + 2)
0010
operation
BC
Process
Process
Data
Data
No
Q3
Q3
DS39761C-page 373
5
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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