PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

7. Module: Interrupts
EXAMPLE 1:
© 2006 Microchip Technology Inc.
ISR @ 0x0008
Foo:
If an interrupt occurs during a two-cycle instruction
that modifies the STATUS, BSR or WREG register,
the unmodified value of the register will be saved
to the corresponding Fast Return (Shadow)
register and upon a fast return from the interrupt,
the unmodified value will be restored to the
STATUS, BSR or WREG register.
For example, if a high priority interrupt occurs
during the instruction, MOVFF TEMP, WREG, the
MOVFF instruction will be completed and WREG
will be loaded with the value of TEMP before
branching to ISR. However, the previous value of
WREG will be saved to the Fast Return register
during ISR branching. Upon return from the
interrupt with a fast return, the previous value of
WREG in the Fast Return register will be written to
WREG. This results in WREG containing the value
it had before execution of MOVFF TEMP, WREG.
Affected instructions are:
MOVFF Fs, Fd
where Fd is WREG, BSR or STATUS;
MOVSF Zs, Fd
where Fd is WREG, BSR or STATUS; and
MOVSS [Zs], [Zd]
where the destination is WREG, BSR or STATUS.
Work around
1. Assembly Language Programming:
CALL
POP
:
:
RETFIE
If any two-cycle instruction is used to modify
the WREG, BSR or STATUS register, do not
use the RETFIE FAST instruction to return
from the interrupt. Instead, save and then
restore WREG, BSR and STATUS via software
as shown in Example 8-1 in the Device Data
Sheet.
Foo, FAST
FAST
ASSEMBLY LANGUAGE INTERRUPT SERVICE
; store current value of WREG, BSR, STATUS for a second time
; clears return address of Foo call
; insert high priority ISR code here
PIC18F6627/6722/8627/8722
2. C Language Programming:
Date Codes that pertain to this issue:
All engineering and production devices.
Alternatively, in the case of MOVFF, use the
MOVF instruction to write to WREG instead. For
example, use:
MOVF
MOVWF
instead of MOVFF TEMP, BSR.
As another alternative, the following work
around shown in Example 1 can be used. This
example overwrites the Fast Return register by
making a dummy call to Foo with the fast
option in the high priority service routine.
The exact work around depends on the com-
piler in use. Please refer to your C compiler
documentation for details.
If using the Microchip MPLAB
define both high and low priority interrupt han-
dler functions as “low priority” by using the
pragma interruptlow
directive instructs the compiler to not use the
RETFIE FAST instruction. If the proper high
priority interrupt bit is set in the IPRx register,
then the interrupt is treated as high priority in
spite of the pragma interruptlow directive.
The code segment shown in Example 2
demonstrates the work around using the C18
compiler. An optimized C18 version, which
illustrates how to reduce the instruction cycle
count to 3, is provided in Example 3.
TEMP, W
BSR
®
DS80221C-page 3
directive.
C18 C Compiler,
This