PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 182
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PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- AC162078 PDF datasheet #2
- PIC18F1230-ISO PDF datasheet #3
- PIC18F1230-ISO PDF datasheet #4
- PIC18F1230-ISO PDF datasheet #5
- Current page: 182 of 318
- Download datasheet (3Mb)
PIC18F1230/1330
TABLE 17-1:
DS39758D-page 182
CMCON
CVRCON
INTCON
PIR1
PIE1
IPR1
PORTA
LATA
TRISA
PORTB
LATB
TRISB
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1:
Name
2:
PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits read as ‘0’.
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0);
otherwise, RA5 reads as ‘0’. This bit is read-only.
PORTB Data Latch Register (Read and Write to Data Latch)
PORTB Data Direction Control Register
GIE/GIEH PEIE/GIEL TMR0IE
TRISA7
LATA7
CVREN
C2OUT
RA7
Bit 7
RB7
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
—
—
—
(1)
(1)
(1)
TRISA6
LATA6
C1OUT
RA6
ADIE
ADIP
Bit 6
ADIF
RB6
—
(1)
(1)
(1)
PORTA Data Latch Register (Read and Write to Data Latch)
PORTA Data Direction Control Register
C0OUT
RA5
CVRR
RCIE
RCIP
RCIF
Bit 5
RB5
(2)
CVRSS
INT0IE
Bit 4
TXIF
TXIE
TXIP
RA4
RB4
—
CMP2IF
CMP2IE
CMP2IP
CVR3
RBIE
Bit 3
RA3
RB3
—
CMP1IE
CMP1IP
TMR0IF
CMP1IF
CMEN2
CVR2
Bit 2
RA2
RB2
CMP0IF
CMP0IE
CMP0IP
CMEN1
INT0IF
CVR1
2009 Microchip Technology Inc.
Bit 1
RA1
RB1
TMR1IE
TMR1IP
TMR1IF
CMEN0
CVR0
RBIF
Bit 0
RA0
RB0
on Page:
Values
Reset
48
48
47
49
49
49
50
49
49
50
49
49
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