AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 4

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
SPECIFICATIONS
Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for
AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1.8 V, T
SUPPLY VOLTAGE
Table 1.
Parameter
DVDD3
DVDD
AVDD3
AVDD
SUPPLY CURRENT
The test conditions for the maximum supply current are the same as the test conditions for the All Blocks Running section of Table 3. The
test conditions for the typical supply current are the same as the test conditions for the Typical Configuration section of Table 3.
Table 2.
Parameter
I
I
I
I
POWER DISSIPATION
Table 3.
Parameter
TYPICAL CONFIGURATION
ALL BLOCKS RUNNING
FULL POWER-DOWN
INCREMENTAL POWER DISSIPATION
1
2
3
DVDD3
DVDD
AVDD3
AVDD
f
f
f
SYSCLK
S
DDS
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
SYSCLK PLL Off
Input Reference On
Output Distribution Driver On
is the sample rate of the output DAC.
is the output frequency of the DDS.
Differential
Single-Ended
LVDS
LVPECL
CMOS
is the frequency at the SYSCLKP and SYSCLKN pins.
Min
3.135
1.71
3.135
3.135
1.71
1.71
Min
Min
Typ
3.30
1.80
3.30
3.30
1.80
1.80
Typ
1.5
190
52
24
24
135
Typ
800
900
13
−105
7
13
70
75
65
A
215
= 25°C, I
Max
3.465
1.89
3.465
3.465
1.89
1.89
Max
3
70
55
55
150
Max
1100
1250
Rev. B | Page 4 of 104
Unit
V
V
V
V
V
V
Unit
mA
mA
mA
mA
mA
mA
Unit
mW
mW
mW
mW
mW
mW
mW
mW
mW
DAC
= 20 mA (full scale), unless otherwise noted.
Test Conditions/Comments
Pin 7, Pin 58
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
Pin 16, Pin 33, Pin 43, Pin 49
Pin 25, Pin 31
Pin 25, Pin 31
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
Test Conditions/Comments
Pin 7, Pin 58
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
Pin 16, Pin 33, Pin 43, Pin 49
Pin 25, Pin 31
Pin 25, Pin 31
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
Test Conditions/Comments
f
distribution output running at 122.88 MHz (all others powered
down); one input reference running at 100 MHz (all others
powered down)
f
outputs configured as LVPECL at 399 MHz; all input references
configured as differential at 100 MHz; fractional-N active (R = 10,
S = 39, U = 9, V = 10)
Conditions = typical configuration; no external pull-up or pull-
down resistors
Conditions = typical configuration; table values show the change
in power due to the indicated operation
f
Single 3.3 V CMOS output with a 10 pF load
SYSCLK
SYSCLK
SYSCLK
= 20 MHz
= 20 MHz
= 1 GHz
1
; high frequency direct input mode
1
1
; f
; f
S
S
= 1 GHz
= 1 GHz
2
2
; f
; f
DDS
DDS
= 399 MHz
= 122.88 MHz
3
; all clock distribution
3
; one LVPECL clock