AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 48

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AD9547/PCBZ

Manufacturer Part Number
AD9547/PCBZ
Description
Clock Generator/Synchronizer Evaluation Board
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9547/PCBZ

Silicon Manufacturer
Analog Devices
Application Sub Type
Network Clock Generator/Synchronizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9547
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9547
Primary Attributes
2 Differential or 4 Single Ended Inputs
Secondary Attributes
CMOS, LVPECL & LVDS Compatible
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9547
Automatic EEPROM Download
Following power-up, assertion of the RESET pin, or a soft reset
(Register 0x0000, Bit 5 = 1), if FncInit[7:3] ≠ 0 (see the Initial M0
to M7 Pin Programming section), the instruction sequence stored
in the EEPROM executes automatically with condition =
FncInit[7:3]. In this way, a previously stored set of register values
downloads automatically on power-up or with a hard or soft
reset. See the EEPROM Conditional Processing section for
details regarding conditional processing and the way that it
modifies the down-load process.
EEPROM Conditional Processing
The condition instructions allow conditional execution of
EEPROM instructions during a download sequence. During
an upload sequence, however, they are stored as is and have
no effect on the upload process.
Note that, during EEPROM downloads, the condition instructions
themselves and the end instruction always execute unconditionally.
Conditional processing makes use of two elements: the condition
(from Condition 1 to Condition 31) and the condition tag board.
The relationships among the condition, the condition tag board,
and the EEPROM controller appear schematically in Figure 48.
Condition is a 5-bit value with 32 possibilities. Condition = 0 is the
null condition. When the null condition is in effect, the EEPROM
controller executes all instructions unconditionally. The remaining
31 possibilities, condition = 1 through condition = 31, modify the
EEPROM controller’s handling of a download sequence.
SCRATCH
EEPROM
PAD
THEY ARE READ FROM
THE SCRATCH PAD.
STORE CONDITION
INSTRUCTIONS AS
THEN TAG DECODED CONDITION
IF B1 ≤ INSTRUCTION ≤ CF,
PROCEDURE
UPLOAD
OCCURRENCE OF
EEPROM CONTROLLER
CONDITION 3 AND
INSTRUCTIONS
CONDITION 13
ARE TAGGED
DOWNLOAD.
WATCH FOR
CONDITION
EXAMPLE
DURING
Figure 48. EEPROM Conditional Processing
PROCEDURE
DOWNLOAD
CONDITION
HANDLER
Rev. B | Page 48 of 104
16
24
8
17
25
1
9
THEN CLEAR ALL TAGS
IF INSTRUCTION = B0,
10
18
26
2
TAG BOARD
CONDITION
11
19
27
INSTRUCTION(S)
3
EXECUTE/SKIP
The condition originates from one of two sources (see Figure 48),
as follows:
If Register 0x0E01, Bits[4:0] ≠ 0, then the condition is the value
stored in Register 0x0E01, Bits[4:0]; otherwise, the condition is
FncInit, Bits[7:3]. Note that a nonzero condition that is present
in Register 0x0E01, Bits[4:0] takes precedence over FncInit,
Bits[7:3].
The condition tag board is a table that is maintained by the
EEPROM controller. When the controller encounters a condition
instruction, it decodes Condition Instruction 0xB1 through Condi-
tion Instruction 0xCF as condition = 1 through condition = 31,
respectively, and tags that particular condition in the condition
tag board. However, Condition Instruction 0xB0 decodes as the
null condition, for which the controller clears the condition tag
board; subsequent download instructions execute unconditionally
(until the controller encounters a new condition instruction).
During download, the EEPROM controller executes or skips
instructions, depending on the value of the condition and the
contents of the condition tag board. Note, however, that condition
instructions and the end instruction always execute uncondi-
tionally during download. If condition = 0, all instructions during
download execute unconditionally. If condition ≠ 0 and there
are any tagged conditions in the condition tag board, the controller
executes instructions only if the condition is tagged.
12
20
28
4
FncInit, Bits[7:3], which is the state of multifunction pins
M3 to M7 at power-up (see the Initial M0 to M7 Pin
Programming section)
Register 0x0E01, Bits[4:0]
13
21
29
5
14
22
30
6
15
23
31
7
IF {NO TAGS} OR {CONDITION = 0}
ELSE
ENDIF
EXECUTE INSTRUCTIONS
IF {CONDITION IS TAGGED}
ELSE
ENDIF
EXECUTE INSTRUCTIONS
SKIP INSTRUCTIONS
0x0E01, BITS[4:0]
IF {0x0E01, BITS[4:0] ≠ 0}
ELSE
ENDIF
REGISTER
CONDITION = 0x0E01, BITS[4:0]
CONDITION = FncInit, BITS[7:3]
5
5
CONDITION
M7
FncInit, BITS[7:3]
5
M3

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