AD9547/PCBZ Analog Devices Inc, AD9547/PCBZ Datasheet - Page 92

• Manufacturer Part Number: AD9547/PCBZ
• Description: Clock Generator/Synchronizer Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of AD9547/PCBZ

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Network Clock Generator/Synchronizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: AD9547
• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9547
• Primary Attributes: 2 Differential or 4 Single Ended Inputs
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9547
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19)
All bits in Register 0x0D00 to Register 0x0D19 are read only. These registers are accessible during EEPROM transactions.
Table 132. EEPROM Status
Address
0x0D00
Table 133. SYSCLK Status
Address
0x0D01
Register 0x0D02 to Register 0x0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0x0209 to Address 0x0210), the appropriate IRQ monitor bit is set to a Logic 1 when the
indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0x0A04 to Address 0x0A0B), the reset all
IRQs bit (Register 0x0A03, Bit 1), or a device reset.
Table 134. IRQ Monitor for SYSCLK
Address
0x0D02
Table 135. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address
0x0D03
Table 136. IRQ Monitor for the Digital PLL
Address
0x0D04
Bit
[7:5]
4
[3:2]
1
0
Bit
[7:3]
2
1
0
Bit
[7:6]
5
4
[3:2]
1
0
Bit
[7:4]
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
Unused
Fault detected
Load in progress
Save in progress
Bit Name
Unused
Stable
Unused
Cal in progress
Lock detected
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK cal complete
SYSCLK cal started
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Bit Name
Switching
Closed
Free run
Holdover
Frequency unlocked
Frequency locked
Phase unlocked
Phase locked
Description
Unused.
An error occurred while saving data to or loading data from the EEPROM.
The control logic sets this bit while data is being read from the EEPROM.
The control logic sets this bit while data is being written to the EEPROM.
Unused.
The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
Unused.
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Description
The control logic holds this bit set while the system clock calibration is in progress.
Description
Unused.
Indicates a SYSCLK PLL state transition from locked to unlocked.
Indicates a SYSCLK PLL state transition from unlocked to locked.
Unused.
Indicates that SYSCLK calibration is complete.
Indicates that SYSCLK calibration has begun.
Description
Indicates that the DPLL is switching to a new reference.
Indicates that the DPLL has entered closed-loop operation.
Indicates that the DPLL has entered free-run mode.
Indicates that the DPLL has entered holdover mode.
Indicates that the DPLL lost frequency lock.
Indicates that the DPLL has acquired frequency lock.
Indicates that the DPLL lost phase lock.
Indicates that the DPLL has acquired phase lock.
Description
Unused.
Indicates a distribution sync event.
Indicates expiration of the watchdog timer.
Indicates a fault during an EEPROM load or save operation.
Indicates successful completion of an EEPROM load or save operation.
Rev. B | Page 92 of 104