IP-XAUIPCS Altera, IP-XAUIPCS Datasheet

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... Altera Transceiver PHY IP Core User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01080-1.11 Altera Transceiver PHY IP Core Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 10.1 December 2010 Subscribe ...

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... Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporation ...

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... Dynamic Reconfiguration Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–12 Clocks, Reset, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 PMA Channel Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 PMA Control and Status Interface Signals–Soft IP Implementation (Optional 4–14 PMA Control and Status Interface Signals–Hard IP Implementation (Optional 4–15 TimeQuest Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 December 2010 Altera Corporation ...

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... Avalon-ST TX Input Data from the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Avalon-ST RX Output Data to the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9 Avalon-MM PHY Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10 PHY Management Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13 Transceiver Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Optional Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Dynamic Partial Reconfiguration I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Chapter 8. Low Latency PHY IP Core Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8– ...

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... Contents Avalon-ST TX and RX Data Interface to the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–6 Avalon-MM PHY Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–7 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8 Optional Status Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–8 Chapter 9. Transceiver Reconfiguration Controller Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2 Steps to Achieve PMA Controls Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Chapter 10. Migrating from Stratix IV to Stratix V XAUI PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10– ...

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... Altera Transceiver PHY IP Core User Guide Contents December 2010 Altera Corporation ...

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... For more information about the Avalon-MM and Avalon-ST protocols, including timing diagrams, refer to the Table 1–1 shows hard and soft implementation support for these IP cores in Stratix devices. Typically, the PCS and PMA are implemented as hard logic, saving FPGA resources and reducing the complexity of verification. In some cases, the PCS is also available in soft logic as Table 1– ...

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... Figure 1–1 illustrates the top level modules that comprise the PHY IP cores. Figure 1–1. Altera Modular PHY Design PHY - Stratix V Avalon-ST Tx and Rx To MAC Avalon-MM To Control & Status Embedded Controller Hard logic for Stratix V, variable for Stratix IV Soft logic for Stratix IV and Stratix V ...

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... TX PLL to create the parallel clock inputs the TX channel PMA and PCS modules. The parallel clocks for each channel are carefully tuned to keep the clock skew below 150 ps. Figure 1–2 December 2010 Altera Corporation ). It converts parallel input data streams to serial OD illustrates bonded mode for Stratix V devices. 1–3 Altera Transceiver PHY IP Core User Guide ...

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... Figure 1–2. Stratix V Device Bonded Mode Clocking Reference clock input pin Tx data Rx data Tx data Rx data Altera Transceiver PHY IP Core User Guide Channel PLL High Low speed frequency parallel Clock Gen clock clock(s) Buffer Tx PLL (CGB) /n, /m Transceiver PMA PCS Ser ...

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... PMA PCS PMA Ser CDR DeSer Data Clock Ser = Serializer DeSer = DeSerializer illustrates mode for Stratix V devices. FPGA-fabric interface Low speed parallel clock(s) PCS Tx PCS Rx PCS Low speed parallel clock(s) PCS Tx PCS Rx PCS Altera Transceiver PHY IP Core User Guide 1–5 ...

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... Note to Table 1–2: (1) You can choose either bonded or non-bonded clocks for the Custom and Low Latency PHY IP cores to meet the requirements of your design. The precise sequence of events that occurs to reset the transceiver PHY depends upon the configuration chosen. The reset sequence for configurations that only include TX channels is far simpler because it does not require the RX analog logic to recover the clock from the input data stream or to perform offset cancellation ...

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... PCS and PMA Control and Status Register Memory Map S Dynamic Reconfiguration S in volume 4 of the Stratix IV Device Handbook for Reset Control and Power Down 1–7 pll_powerdown phy_mgmt_clk_reset tx_ready to / from user logic rx_ready in volume 2 of the Stratix V Device Altera Transceiver PHY IP Core User Guide ...

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... Figure 1–6. Serial Loopback FPGA Fabric To FPGA fabric for verification Unsupported Features The protocol-specific PHYs are not supported in SOPC Builder in the current release. Altera Transceiver PHY IP Core User Guide 1–2.) PCI Express Base Specification. Figure 1–6 Transceiver Tx PMA Tx PCS Serializer Rx PMA ...

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... This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications ...

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... For some IP cores, this flow generates a complete example design and testbench. MegaWizard Plug-In Manager Flow The MegaWizard Plug-In Manager flow allows you to customize your IP core and manually integrate the function into your design. Specifying Parameters To specify IP core parameters with the MegaWizard Plug-In Manager, follow these steps: 1 ...

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... Chapter 2: Getting Started MegaWizard Plug-In Manager Flow 3. To select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the “Parameter Settings” chapter in this document. ...

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... Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project. You can also turn on Automatically add Quartus II IP Files to all projects. You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments ...

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... Controller S Management In this configuration, 10GBASE-R PHY IP core includes a soft PCS and a hard PMA. The soft PCS connects to an Ethernet MAC running at 156.25 Mbps and transmits data to a hard 10 Gbps transceiver PMA running at 10.3125 Gbps in a Stratix IV GT device. December 2010 Altera Corporation 3 ...

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... Figure 3–2 shows the 10GBASE-R PHY IP core available for Stratix V devices. Both the PCS and PMA of the 10GBASE-R PHY are available as hard IP blocks in Stratix V, devices saving FPGA resources. Figure 3–2. 10GBASE-R PHY with Hard PCS with Hard PMA in Stratix V Devices ...

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... No ordering codes or license files are required for Stratix V devices. Device Family Support IP cores provide either final or preliminary support for target Altera device families. These terms have the following definitions: Final support—Verified with final timing models for this device. ...

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... PMA controller and reconfiguration IP cores for other protocols in the same transceiver quad. This option is available in Stratix IV devices. Specifies the starting channel number. Must multiple of 4. You only need to set this parameter if you are using external PMA and reconfiguration modules. ...

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... SOPC Builder User Guide. 10GBASE-R Top-Level Signals rx_serial_data <n> tx_serial_data <n> gxb_pdn pll_locked pll_pdn cal_blk_pdn rx_oc_busy cal_blk_clk reconfig_to_gxb[3:0] reconfig_from_gxb[16:0] rx_block_lock rx_hi_ber pll_ref_clk 3–5 Transceiver Serial Data Signals for External PMA and Reconfiguration Stratix IV only Status Clock f Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Description Contains 8 lanes of data and control for XGMII. Each lane consists of 8 bits of data and 1 bit of control. Lane 0–[7:0]/[8] ■ Lane 1–[16:9]/[17] ■ Lane 2–[25:18]/[26] ■ ...

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... FIFO between the MAC and SDR XGMII RX interface. XGMII Signal Name xgmii_sdr_data[7:0] xgmii_sdr_ctrl[0] xgmii_sdr_data[15:8] 3–7 Description Lane 5 control Lane 6 data Lane 6 control Lane 7 data Lane 7 control Description Lane 0 data Lane 0 control Lane 1 data Altera Transceiver PHY IP Core User Guide ...

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... Avalon-MM Interface The Avalon-MM module provides access to the PCS and PMA registers, the Transceiver Reconfiguration IP core, and the Low Latency PHY Controller IP core. PHY management block includes Avalon-MM master and slave interfaces and acts as a bridge. It transfers commands received on its Avalon-MM slave interface to its Avalon-MM port. Table 3– ...

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... Register Descriptions Table 3–10 specifies the registers that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers. Table 3–10. 10GBASE-R Register Descriptions (Part Word Bit R/W Addr ...

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... Table 3–10. 10GBASE-R Register Descriptions (Part Word Bit R/W Addr 0x061 [31:0] RW pma_serial_loopback 0x063 [31:0] R pma_rx_signaldetect 0x064 [31:0] RW pma_rx_set_locktodata 0x065 [31:0] RW pma_rx_set_locktoref 0x066 [31:0] R pma_rx_is_lockedtodata 0x067 [31:0] R pma_rx_is_lockedtoref 0x080 [31:0] RW INDIRECT_ADDR [2] RW RCLR_ERRBLK_CNT 0x081 [3] RW RCLR_BER_COUNT [0] R PCS_STATUS [1] R HI_BER ...

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... Chapter 3: 10GBASE-R PHY IP Core Interfaces Table 3–10. 10GBASE-R Register Descriptions (Part Word Bit R/W Addr [5:0] R BER_COUNT 0x083 [7:0] R ERROR_BLOCK_COUNT Status Interface Table 3–11 describes signals that provide status information. Table 3–11. Status Outputs Signal Name Direction Output block_lock Output hi_ber Clocks, Reset, and Powerdown The phy_mgmt_clk_reset signal is the global reset that resets the entire PHY ...

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... MHz clock. illustrates the clock generation and distribution for Stratix IV devices. Figure 3–4. Stratix IV GT Clock Generation and Distribution 10GBASE-R Transceiver Channel - Stratix xgmii_tx_clk RX 64 xgmii_rx_clk 156.25 MHz Altera Transceiver PHY IP Core User Guide PCS TX PCS (soft IP) (hard IP) /2 257.8125 516.625 MHz ...

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... Chapter 3: 10GBASE-R PHY IP Core Interfaces Figure 3–5 illustrates the clock generation and distribution for Stratix V devices. Figure 3–5. Stratix V Clock Generation and Distribution 10GBASE-R Hard IP Transceiver Channel - Stratix xgmii_tx_clk RX 64 xgmii_rx_clk 156.25 MHz 1 To ensure proper functioning of the PCS, the maximum PPM difference between the pll_ref_clk and xgmii_tx_clk clock inputs is 100 PPM ...

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... External PMA Control and Reconfig Interface Table 3–14 describes the additional top-level signals 10GBASE-R PHY IP core when the configuration includes external modules for PMA control and reconfiguration. You enable this configuration by turning on Use external PMA control and reconfig available for Stratix IV GT devices ...

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... TimeQuest Timing Constraints Example 3–1 for the 10GBASE-R IP core. To pass timing analysis, you must decouple the clocks in different time domains. Be sure to verify the each clock domain is correctly buffered in the top level of your design. You can find the .sdc file in your top-level working directory. This is the same directory that includes your top-level .v or .vhd file. Example 3– ...

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... Set Input Transition #************************************************************** 1 This .sdc file is only applicable to the 10GBASE-R PHY IP core when compiled in isolation. You can use reference to help in creating your own .sdc file. Altera Transceiver PHY IP Core User Guide Chapter 3: 10GBASE-R PHY IP Core TimeQuest Timing Constraints December 2010 Altera Corporation ...

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... PHY component on a PCB to one meter. Figure 4–1 illustrates the top-level blocks of the XAUI PHY for Stratix Stratix V devices. Figure 4–1. XAUI PHY with Hard IP PCS and PMA in Stratix Stratix V Devices Arria II GX, Cyclone IV GX, Stratix GT, or Stratix V FPGA SDR XGMII 72 bits @ 156.25 Mbps Avalon-MM Control & ...

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... Preliminary support—Verified with preliminary timing models for this device. Table 4–2 shows the level of support offered by the XAUI IP core for Altera device families. Table 4–2. Device Family Support Arria II GX–hard PCS and hard PMA Cyclone IV GX–hard PCS and hard PMA Stratix IV GX and GT devices– ...

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... Parameter Settings Parameter Settings To configure the XAUI IP core in the parameter editor, click Installed Plug-Ins > Interfaces >Ethernet> XAUI PHY v10.1. This section describes the XAUI PHY IP core parameters, which you can set using the parameter editor. Table 4–4. General Options Name Arria II GX ...

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... Configurations Figure 4–2 illustrates one configuration of the XAUI IP core. As this figure illustrates, if your variant includes a single instantiation of the XAUI IP core, the transceiver reconfiguration control logic is included in the XAUI PHY IP core. Figure 4–2. XAUI PHY Using One Channel Low Latency PHY Controller ...

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... Interfaces Interfaces Figure 4–3 illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementation which is available for Stratix IV GX and Stratix V devices. illustrates the top-level signals of the XAUI PHY IP core for the hard IP implementation which is available for Stratix IV GX devices. With the exception of the optional signals available for debugging, the pinout of the two implementations is nearly identical ...

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... Figure 4–4 illustrates the top-level signals of the XAUI PHY IP core for the hard IP implementation which is available for Arria II GX, Cyclone IV GX, and Stratix IV GX devices. Figure 4–4. XAUI Top-Level Signals–Hard IP PCS and PMA XAUI Top-Level Signals Hard IP Implementation xgmii_tx_dc[71:0] ...

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... To meet the bandwidth requirements, the datapath is eight bytes wide with eight control bits, instead of the standard four bytes of data and four bits of control. The XAUI IP core treats the datapath as two, 32-bit data buses and includes logic to interleave them, starting with the low-order bytes. Figure 4– ...

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... The Avalon-MM PHY management block includes master and slave interfaces. This component acts as a bridge. It transfers commands received on its Avalon-MM slave interface to its Avalon-MM port. This interface provides access to the PCS and PMA registers, the Transceiver Reconfiguration, and the Low Latency PHY Controller IP cores. Table 4–8 Management interface. Table 4– ...

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... Chapter 4: XAUI PHY IP Core Interfaces Table 4–9. XAUI PHY IP Core Registers (Part Word Bits R/W Addr W reset_control (write) 0x042 [1:0] R reset_status(read) [31:4,0] RW reset_fine_control [1] RW reset_tx_digital 0x044 [2] RW reset_rx_analog [3] RW reset_rx_digital 0x061 [31:0] RW phy_serial_loopback 0x063 [31:0] R pma_rx_signaldetect 0x064 [31:0] RW pma_rx_set_locktodata 0x065 [31:0] ...

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... Table 4–9. XAUI PHY IP Core Registers (Part Word Bits R/W Addr [31:2] — Reserved [1] tx_digital reset 0x081 RW [0] rx_digital reset [31:4] — Reserved 0x082 [3:0] RW invpolarity[3:0] [31:4] — Reserved 0x083 [3:0] RW invpolarity[3:0] [31:16] — Reserved [15:8] syncstatus[7:0] 0x084 R [7:0] patterndetect[7:0] [31:16] — ...

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... Chapter 4: XAUI PHY IP Core Interfaces Table 4–9. XAUI PHY IP Core Registers (Part Word Bits R/W Addr [31:8] — Reserved phase_comp_fifo_error[3: 0] [7:4] 0x086 R, sticky rlv[3:0] [3:0] [31:16] — Reserved [15:8] rmfifodatainserted[7:0] 0x087 R, sticky rmfifodatadeleted[7:0] [7:0] [31:8] — Reserved rmfifoempty[3:0] [7:4] R, 0x088 sticky ...

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... Table 4–11 describes the signals in the reconfiguration interface. If your XAUI PHY IP core includes a single transceiver quad, these signals are internal to the core. If your design uses more than one quad, they are external. ...

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... Figure 4–6. Clock Inputs and Outputs, Hard PCS phy_mgmt_clk pll_ref_clk xgmii_tx_clk xgmii_rx_clk Figure 4–7 illustrates the clock inputs and outputs for the XAUI IP cores with soft PCS and PMA blocks. Figure 4–7. Clock Inputs and Outputs, Soft PCS phy_mgmt_clk pll_ref_clk xgmii_tx_clk xgmii_rx_clk Table 4– ...

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... XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP core. Table 4–14. Optional Control and Status Signals—Soft IP Implementation, Stratix IV GX and Stratix V Devices Signal Name rx_channelaligned ...

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... XAUI PHY. In such cases, you can include the required signal in the top-level module of your XAUI PHY IP core. Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part Signal Name rx_invpolarity[3:0] ...

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... Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part Signal Name rx_patterndetect[7:0] rx_rmfifodatadeleted[7:0] rx_rmfifodatainserted[7:0] rx_runningdisp[7:0] rx_syncstatus[7:0] rx_phase_comp_fifo_error[3:0] tx_phase_comp_fifo_error[3:0] rx_rlv[3:0] TimeQuest Timing Constraints Example 4–1 analysis you must decouple the clocks in different time domains. Example 4–1. Synopsys Design Constraints for Clocks ...

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... This .sdc file is only applicable to the XAUI IP core when compiled in isolation. You can use reference to help in creating your own .sdc file. December 2010 Altera Corporation 4–17 Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 4: XAUI PHY IP Core TimeQuest Timing Constraints December 2010 Altera Corporation ...

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... For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon Interface Interlaken operates on 64-bit data words which are striped round robin across the lanes to reduce latency. Striping renders the interface independent of exact lane count. The protocol accepts packets on 256 logical channels. Packets are split into small bursts which can optionally be interleaved ...

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... Parameter Settings To configure the Interlaken IP core in the parameter editor, click Installed Plug-Ins > Interfaces > Interlaken > Interlaken PHY v10.1. The Interlaken IP core is only available when you select the Stratix V device family. This section describes the Interlaken PHY parameters, which you can set using the parameter editor ...

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... Specifies the number of lanes in a link over which data is striped. Specifies the number of words in a metaframe. The default value is 2048. Optional Ports When you turn this option on, rx_parallel_data[71:69] are included in the top-level module. These optional signals report the status of word and synchronization locks and CRC32 errs ...

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... Table 5–4. Avalon-ST TX Signals Signal Name Direction Sink tx_parallel_data[63:0] Sink tx_parallel_data[64] Sink tx_parallel_data[65] Source tx_ready Source tx_datain_bp Altera Transceiver PHY IP Core User Guide Component Interface Tcl Reference (Note 1) Interlaken Top-Level Signals tx_parallel_data<n>[65:0] tx_serial_data<n> tx_ready rx_serial_data<n> tx_datain_bp<n> tx_clkout<n> tx_user_clkout rx_parallel_data<n>[71:0] rx_ready rx_clkout< ...

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... The RX interface has a ready latency of 1 cycle so that Sink rx_dataout<n>[63:0] and rx_ctrlout are valid the cycle after rx_dataout_bp<n> is asserted. Master channel rx_clkout is available when you do not create the Output optional rx_coreclkin. 5–5 Description Altera Transceiver PHY IP Core User Guide ...

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... RW reset_ch_bitmask W reset_control (write) 0x042 [1:0] R reset_status(read) Altera Transceiver PHY IP Core User Guide Direction Input Avalon-MM clock input. Global reset signal that resets the entire interlaken PHY. A positive Input edge on this signal triggers the reset controller. Input 9-bit Avalon-MM address. Input Input data ...

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... RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>. When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. 5–7 Description 1–2, performs a standard Altera Transceiver PHY IP Core User Guide ...

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... PLL interface. Table 5–8. Serial Interface Signal Name pll_ref_clk TX and RX Serial Interface Table 5–9 describes the signals in the chip-to-chip serial interface. Table 5–9. Serial Interface Signal Name tx_serial_data rx_serial_data Altera Transceiver PHY IP Core User Guide Stratix V Device Registers Asserted when the first alignment pattern is found ...

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... The top-level project directory. The top-level design file. A list of all files necessary for Quartus II compilation. A Block Symbol File (.bsf) for your Interlaken PHY. The directory that stores the HDL files that define the Interlaken PHY IP core. These files are used for synthesis. 5–9 Description ...

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... For more information about simulating with ModelSim, refer to the ModelSim Support Altera Transceiver PHY IP Core User Guide Description The top-level static Verilog HDL file for the Interlaken PHY IP core. It includes parameterized port widths. Generates waitrequest for alt_interlaken_pcs. The transceiver core and memory-mapped logic for specified number of lanes for PMA and PLLs ...

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... Chapter 5: Interlaken PHY IP Core Simulation Testbench Example 5–1. Testbench Variables ################################################################################# ## ## Set your language and top level design name here ## ################################################################################# # language = verilog (verilog variant of the PHY IP) or vhdl (vhdl variant of the PHY IP) # defaulted to verilog set language verilog ################################################################################# ## ## Set your top level design name here ## ################################################################################# # dut_name = top-level Verilog variant name as generated by Qmegawiz set dut_name < ...

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... Altera Transceiver PHY IP Core User Guide Chapter 5: Interlaken PHY IP Core Simulation Testbench December 2010 Altera Corporation ...

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... Gbps. Figure 6–1 illustrates the top-level blocks of the PCI Express PHY (PIPE) for Stratix V GX devices. Figure 6–1. PCI Express PHY (PIPE) with Hard IP PCS and PMA in Stratix V GX Devices Avalon-ST Tx and Rx Avalon-ST PIPE from PCI Express ...

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... To configure the PCI Express PHY (PIPE) IP core in the parameter editor, click Installed Plug-Ins > Interfaces > PCI Express > PCI Express PHY (PIPE) v10.1. The PCI Express PHY PIPE IP core is only available when you select the Stratix V device family. This section describes the PCI Express PHY PIPE parameters, which you can set using the parameter editor. Table 6– ...

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... Note to Figure 6–2: (1) <n> is the number of lanes. The PHY (PIPE) supports ×1, ×4, ×8 operation. <d> is the total deserialization factor from the input pin to the PHYMAC interface. <s> is the symbols size. 1 The block diagram shown in the GUI labels the external pins with the interface type and places the interface name inside the box ...

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... Data and control indicator for the received data. When 0, indicates that Sink pipe_txdata is data, when 1, indicates that pipe_txdata is control. Dir This is RX parallel data driven from the PHY (PIPE). The ready latency on Source this interface that the MAC must be able to accept data as soon as the PHY comes out of reset. ...

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... Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Figure 6–3 illustrates the internal modules of the PCI Express PHY (PIPE) IP core. Figure 6–3. PCI Express PIPE IP Core PCI Express PIPE and Avalon-MM Control Interface for Non-PIPE Functionality PIPE reset Clocks Tx Data, Datak PIPE Control ...

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... Table 6–7 describes the registers that you can access over the Avalon-MM PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers. Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part Word Bits R/W ...

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... Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part Word Bits R/W Register Name Addr [31:4,0] RW reset_fine_control [1] RW reset_tx_digital 0x044 [2] RW reset_rx_analog [3] RW reset_rx_digital 0x061 [31:0] RW phy_serial_loopback 0x063 [31:0] R pma_rx_signaldetect 0x064 [31:0] RW pma_rx_set_locktodata 0x065 ...

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... Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part Word Bits R/W Register Name Addr [31:6] R Reserved rx_bitslipboundary [5:1] R selectout 0x081 [0] R rx_phase_comp_fifo_error [31:1] R Reserved 0x082 [0] RW tx_phase_comp_fifo_error [31:6] RW Reserved tx_bitslipboundary_selec [5: 0x083 [0] RW tx_invpolarity [31:1] RW Reserved 0x084 [0] RW rx_invpolarity [31:4] ...

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... Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Table 6–7. PCI Express PHY (PIPE) IP Core Registers (Part Word Bits R/W Register Name Addr [31:20] R Reserved [19:16] R rx_rlv [15:12] R rx_patterndetect [11:8] R rx_disperr 0x086 [7:4] R rx_syncstatus [3:0] R rx_errdetect PIPE Interface Table 6–8 describes the signals in the PIPE interface. ...

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... Note to Table 6–8: (1) <n> is the number of lanes. The PHY (PIPE) supports ×1, ×4, ×8 operation. Altera Transceiver PHY IP Core User Guide When asserted for one cycle, sets the 8B/10B encoder output running disparity to negative. Used when transmitting the compliance pattern. Refer ...

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... Chapter 6: PCI Express PHY (PIPE) IP Core Interfaces Figure 6–4 illustrates the pipe_pclk switching from Gen1 to Gen2 and back to Gen1. Figure 6–4. Rate Switch from Gen1 to Gen2 pipe_pclk pipe_rate pipe_phystatus[<n>-1:0] Note to Figure 6–4: (1) Time T1 is pending characterization. (2) <n> is the number of lanes. ...

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... VHDL. All the underlying files are written Verilog or System Verilog. To enable simulation using a VHDL-only ModelSim license, the underlying Verilog and System Verilog files for the PCIe PIPE PHY are encrypted so that they can be used with the top-level VHDL wrapper without purchasing a mixed-language simulator. ...

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... Simulation Example 6–1 Example 6–1. Simulation Variables ################################################################################# ## ## Set your language and top level design name here ## ################################################################################# # language = verilog (verilog variant of the PHY IP) or vhdl (vhdl variant of the PHY IP) # defaulted to verilog set language verilog ################################################################################# ## ## Set your top level design name here ## ################################################################################# # dut_name = top-level Verilog variant name as generated by Qmegawiz set dut_name < ...

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... Altera Transceiver PHY IP Core User Guide Chapter 6: PCI Express PHY (PIPE) IP Core Simulation December 2010 Altera Corporation ...

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... The Altera Custom PHY IP core is a generic PHY that you can customize for use in Stratix V FPGAs. You can connect your application’s MAC-layer logic to the Custom PHY to transmit and receive data at rates of 0.600–8.5 Gbps. You can parameterize the physical coding sublayer (PCS) to include the functions that your application requires. The following functions are available: ■ ...

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... Preliminary support—Verified with preliminary timing models for this device. Table 7–1 shows the level of support offered by the Custom PHY IP core for Altera device families Table 7–1. Device Family Support Arria II GX Arria II GZ HardCopy IV GX Stratix IV GX Stratix V devices–hard PCS and hard PMA ...

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... When you turn this option off, the TX and RX interfaces are configured as a single data and control bus, regardless of the number of lanes. The layout and transmission of the TX and RX buses is little endian. Refer to 7–3 Description Figure 7–2. Figure 7–3. Altera Transceiver PHY IP Core User Guide ...

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... Enable manual disparity control On/Off Create optional 8B/10B status On/Off port Altera Transceiver PHY IP Core User Guide lists the settings available on the 8B/10B tab. Value Enable this option if your application requires 8B/10B encoding and decoding. This option on adds the tx_datak<n>, rx_datak<n>, and rx_runningdisp< ...

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... Avalon-MM interface. Word aligner starts searching for the alignment pattern as soon as this control signal is asserted. Bit Slip Mode—You can use bit slip mode to shift the word ■ boundary using the Avalon-MM interface. For every rising edge of the rx_bitslip signal, the word boundary is shifted by 1 bit ...

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... The rate match FIFO compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip (SKP) symbols or ordered-sets from the inter-packet gap (IPG) or idle streams. It deletes SKP symbols or ordered-sets when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency ...

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... PHY. Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern (bits 0–9). The skip pattern must have neutral disparity. Enter a 10-bit skip pattern (bits 10–19) and a 10-bit control pattern (bits 0– ...

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... Deserializer actual width Single Double f For a description of the Analog options, refer the to page 8–4. Interfaces Figure 7–4 illustrates the top-level signals of the Custom PHY IP core. Figure 7–4. Custom PHY Top-Level Signals Avalon-ST Tx from MAC Optional Avalon- MAC Optional Avalon-MM PHY Management ...

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... On the Enable disparity control option on the 8B/10B tab. Direction This is RX parallel data driven from the Custom PHY IP core. The ready latency on this interface that the MAC must be able to accept Source data as soon as the PHY comes out of reset. Data driven from this interface is always valid ...

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... This status signal indicates the disparity of the incoming data. This signal is created if you turn On the Enable byte ordering block control option on the Byte Order tab. A byte ordering operation occurs Input whenever rx_enabyteord is asserted. To perform multiple byte ordering operations, deassert and reassert rx_enabyteord. Reset Controller ...

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... Table 7–12 specifies the registers that you can access over the PHY management interface using word addresses and a 32-bit embedded processor. A single address space provides access to all registers. Table 7–12. Low Latency PHY IP Core Registers (Part Word Bits R/W Register Name ...

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... Reserved. When set, indicates an RX phase compensation FIFO error. From block: RX phase Compensation FIFO This is an output from the bit slip word aligner which shows the number of bits slipped. From block: Word aligner. Chapter 7: Custom PHY IP Core ...

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... From block: TX phase Compensation FIFO Reserved. When set, the TX interface inverts the polarity of the TX data. To block: 8B/10B encoder. Sets the number of bits that the TX bit slipper needs to slip. To block: Word aligner. When set, the RX channels inverts the polarity of the received data. To block: 8B/10B decoder. ...

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... When asserted, enables a circuit to detect a downstream receiver. Input It is used for the PCI Express protocol. This signal is used for bit slip word alignment mode. It selects the Input number of bits that the TX block must slip to achieve a deterministic latency. When asserted, indicates that the received 10-bit code or data Output group has a disparity error ...

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... December 2010 Altera Corporation (Note 1) Direction This signal is used for bit slip word alignment mode. It reports Output the number of bits that the RX block slipped to achieve a deterministic latency. Table 7–16 describes the signals in the Direction Reconfiguration signals from the Transceiver Reconfiguration Sink Controller ...

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... Altera Transceiver PHY IP Core User Guide Chapter 7: Custom PHY IP Core Interfaces December 2010 Altera Corporation ...

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... Figure 8–1. Low-Latency PHY IP Core—Stratix IV and Stratix V Devices Stratix IV or Stratix V FPGA to MAC to Embedded Controller Because the Low latency PHY IP core bypasses much of the standard PCS, it minimizes the PCS latency. low latency PCS. Table 8–1. TX Datapath Latency Block TX Phase Compensation FIFO Byte Serializer ...

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... Altera Transceiver PHY IP Core User Guide Preliminary No support. Value This IP core is only available Stratix V. Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices are not supported in this release. Number of channels, default value is 1. For Stratix V devices, the valid range is 1–24 for the non-bonded mode and 1–5 for the bonded mode ...

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... FPGA fabric clock, the FPGA fabric RX interface clock, or the input reference clock. When set, the word aligner operates in bit-slip mode. This option is available for Stratix V devices using the 10G PCS. This option selects the higher throughput 10G PCS rather than the standard PCS ...

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... Altera Transceiver PHY IP Core User Guide Value Parameters for Stratix IV and Derivatives Allows you to choose a clock multiplier unit (CMU) or auxiliary transmit (ATX) PLL. The CMU PLL is designed to achieve low TX channel-to-channel skew. The ATX PLL is designed to improve jitter performance. This option is only available for Stratix IV GX devices ...

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... RX termination resistance OCT_120_OHMS OCT_150_OHMS Receiver DC gain 0–4 Receiver static equalizer setting: 0–15 Interfaces Figure 8–2 illustrates the top-level signals of the Low Latency PHY IP core. Figure 8–2. Top-Level PMA Signals Avalon-ST Tx and Rx to and from MAC Stratix IV Only Avalon-MM PHY Management Interface ...

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... Output receive data from the MAC. This signal is only used in Stratix IV devices. This is RX parallel data driven by the Low Latency PHY IP core. Data Source driven from this interface is always valid. This is the ready signal for the RX interface. The ready latency on this ...

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... RX data, and that the RX CDR has changed from LTR to LTD mode. Bit <n> corresponds to channel <n>. When asserted, indicates that the RX CDR PLL is locked to the reference clock. Bit <n> corresponds to channel <n>. 8–7 Description Description Altera Transceiver PHY IP Core User Guide ...

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... Signal Name rx_serial_data[<n-1>:0] tx_serial_data [<n-1>:0] Note to Table 8–8: (1) <n> is the number of modules connecting to the Transceiver Reconfiguration IP core. Optional Status Interface Table 8–9 describes the signals that comprise the optional status interface. Table 8–9. Optional Status Interface Signal Name rx_clkout[<n-1>:0] rx_is_lockedtodata[< ...

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... You can access the dynamic reconfiguration functionality using an embedded processor to drive the Avalon-MM PHY management interface of the Transceiver Toolkit, the XAUI PHY IP core or the 10GBASE-R PHY IP core as appropriate. The Analog Control and Offset Cancellation modules translate device independent commands received on their Avalon-MM slave interface to the Reconfiguration Controller module which converts them into device dependent commands on the dynamic reconfiguration interface ...

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... Reserved 0x10B [4:0] RW tx_rx_word_offset Altera Transceiver PHY IP Core User Guide which illustrates the critical signals for the reset of a Register Name The logical channel address. Must be specified when performing dynamic updates. The physical channel address. Error. When asserted, indicates an error. This bit is asserted if any of the following conditions occur: ■ ...

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... December 2010 Altera Corporation Register Name Reconfiguration data. For complete information about the EyeQ interface and registers refer to, “EyeQ Interface Register Mapping” in the Stratix IV Dynamic Reconfiguration volume 2 of the Stratix IV Device Handbook. 9–3 Description — chapter in Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 9: Transceiver Reconfiguration Controller Steps to Achieve PMA Controls Reconfiguration December 2010 Altera Corporation ...

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... Custom PHY ■ XAUI PHY This section lists the differences between the parameters and signals for the XAUI PHY IP core and the ALTGX megafunction when configured in the XAUI functional mode. Parameter Differences Table 10–1 lists the XAUI PHY parameters and the corresponding ALTGX megafunction parameters. Table 10– ...

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... Table 10–2. Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals (Part Stratix IV GX Devices Signal Name pll_inclk rx_cruclk cal_blk_clk reconfig_clk Altera Transceiver PHY IP Core User Guide XAUI PHY Parameter Name 1000) Not available as parameters in the MegaWizard interface —Not available as parameters in the MegaWizard interface ...

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... Width 1 — [3:0] [63:0] [63:0] [3:0] — — — — — — — — — — — [<n>*2 – 1:0] — — — [<n>*2 – 1:0] [<n>*2 – 1:0] — — — — — — Altera Transceiver PHY IP Core User Guide ...

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... PCI Express (PIPE) functional mode. Parameter Differences Table 10–3 lists the PCI Express PHY (PIPE) parameters and the corresponding ALTGX megafunction parameters. Table 10–3. Comparison of ALTGX Megafunction and PCI Express PHY (PIPE) Parameters (Part ALTGX Parameter Name (Default Value) Number of channels Channel width Subprotocol ...

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... Stratix V GX/GS devices. PIPE standard ports remain, but are now prefixed with pipe_. Clocking options are simplified to match the PIPE 2.0 specification. Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part (Note 1) Stratix IV GX Device Signal Name ...

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... Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part (Note 1) Stratix IV GX Device Signal Name pll_powerdown rx_analogreset rx_digitalreset tx_digitalreset gxb_powerdown cal_blk_powerdown Not available Not available tx_datain tx_ctrlenable tx_detectrxloop tx_forcedispcompliance tx_forceelecidle txswing tx_pipedeemph[0] tx_pipemargin[2:0] rateswitch[0] ...

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... Chapter 10: Migrating from Stratix IV to Stratix V PCI Express PHY (PIPE) Table 10–4. PCIe PHY (PIPE) Correspondence between Stratix IV GX Device and Stratix V Device Signals (Part (Note 1) Stratix IV GX Device Signal Name rx_locktodata rx_locktorefclk tx_invpolarity rx_errdetect rx_disperr rx_patterndetect tx_phase_comp_fifo_error rx_phase_comp_fifo_error rx_signaldetect rx_rlv ...

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... Custom PHY This section lists the differences between the parameters and signals for the Custom PHY IP core nd the ALTGX megafunction when configured in the Basic functional mode. Parameter Differences Table 10–5 lists the Custom PHY parameters and the corresponding ALTGX megafunction parameters. ...

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... Avalon-ST Tx Interface Avalon-ST Rx Interface High Speed Serial I/O 10–9 Width [<p>-1:0] [<d><n>-1:0] [<d><n>-1:0] [<d><n>-1:0] [<d><n>-1:0] [<d/8><n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] [<n>-1:0] Altera Transceiver PHY IP Core User Guide ...

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... Altera Transceiver PHY IP Core User Guide Chapter 10: Migrating from Stratix IV to Stratix V Custom PHY December 2010 Altera Corporation ...

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... December 1.11 2010 Removed table providing ordering codes for the Interlaken PHY IP core. Ordering codes are ■ not required for Stratix V devices using the hard implementation of the Interlaken PHY. Added note to 10GBASE-R release information table stating that “No ordering codes or ■ ...

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... Removed rx_offset_cancellation_done signal. Internal reset logic determines when ■ offset cancellation has completed. Removed support for Stratix IV GX devices. ■ Reconfiguration is now integrated into the XAUI PHY IP core and 10GBASE-R PHY IP core. ■ December 1.1 2010 Revised register map to show word addresses instead of a byte offset from a base address. ...

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... Options menu. Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, “Typographic Conventions.” Info–3 and Table 6–7 on page 6–6. The base Address www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature nacomp@altera.com authorization@altera.com Altera Transceiver PHY IP Core User Guide SPR ...

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... Altera Transceiver PHY IP Core User Guide Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. The suffix n denotes an active-low signal. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears ...