IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 80

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–2
Performance and Resource Utilization
Parameter Settings
Table 7–2. General Options (Part 1 of 2)
Altera Transceiver PHY IP Core User Guide
Device family
Mode of operation
Number of lanes
FPGA fabric transceiver
interface width
Enable bonding
Data rate
Input clock frequency
Enable TX Bitslip
General Options
Name
■
Table 7–1
device families
Table 7–1. Device Family Support
Accurate resource utilization numbers are not available at this time.
To configure the Custom PHY IP core in the parameter editor, click Installed Plug-Ins
> Interfaces > Transceiver PHY > Custom PHY v10.1.
The General Options tab allows you to set the basic parameters of your PHY.
Table 7–2
Arria II GX
Arria II GZ
HardCopy IV GX
Stratix IV GX
Stratix V devices–hard PCS and hard PMA
Other device families
Preliminary support—Verified with preliminary timing models for this device.
shows the level of support offered by the Custom PHY IP core for Altera
lists the settings available on the General Options tab.
Arria II GX
Arria II GZ
HardCopy IV
Stratix IV
Stratix V
Duplex
TX
RX
1–32
8,10,16,20,
32,40
On/Off
600–8500 Mbps Specifies the data rate.
60–700 MHz
On/Off
Value
Device Family
Additional Options
Specifies the device family.
You can select to transmit data, receive data, or both. Stratix IV only
supports Duplex mode in the current release.
The total number of lanes in each direction.
Specifies the total serialization factor, from an input or output pin to
the MAC-layer logic.
When enabled, a single clock drives multiple lanes, reducing clock
skew.
Specifies the frequency of the PLL input reference clock.
When enabled, the TX bitslip word aligner is operational.
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
No support
Description
Performance and Resource Utilization
December 2010 Altera Corporation
Chapter 7: Custom PHY IP Core
Support