IP-XAUIPCS Altera, IP-XAUIPCS Datasheet - Page 109

• Manufacturer Part Number: IP-XAUIPCS
• Description: IP CORE - XAUI PHY
• Manufacturer: Altera

Specifications of IP-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 10: Migrating from Stratix IV to Stratix V
XAUI PHY
Table 10–2. Correspondences between XAUI PHY Stratix IV GX and Stratix V Device Signals (Part 2 of 3)
December 2010 Altera Corporation
coreclkout
rx_coreclk
tx_coreclk
Not available
Not available
rx_datain
tx_datain
rx_dataout
tx_dataout
gxb_powerdown
pll_powerdown
rx_analogreset
rx_digitalreset
tx_digitalreset
pll_locked
rx_locktorefclk
rx_locktodata
rx_pll_locked
rx_freqlocked
rx_phase_comp_fifo_error
tx_phase_comp_fifo_error
cal_blk_powerdown
rx_syncstatus
rx_patterndetect
rx_invpolarity
rx_ctrldetect
rx_errdetect
rx_disperr
tx_invpolarity
rx_runningdisp
rx_rmfifofull
rx_rmfifoempty
rx_rmfifodatainserted
rx_rmfifodatadeleted
Signal Name
Stratix IV GX Devices
1
[<n> – 1:0]
[<n> – 1:0]
[<n>-1:0]
[16<n> -1:0]
[16<n> – 1:0]
[<n> -1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[<n>-1:0]
[<n> -1:0]
[<n> -1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[<n>/4 – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
[<n> – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
[<n> – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
[2<n> – 1:0]
Optional Tx and Rx Status Ports
Width
—
—
—
Data Ports
xgmii_rx_clk
xgmii_tx_clk
rx_pma_ready
tx_pma_ready
xaui_rx_serial
xgmii_tx_dc
xgmii_rx_dc
xaui_tx_serial
rx_digitalreset
tx_digitalreset
rx_syncstatus
rx_errdetect
rx_disperr
Not available, however you can access
them through the Avalon-MM PHY
management interface.
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Not available
Signal Name
Stratix V Devices
Altera Transceiver PHY IP Core User Guide
1
1
1
1
[3:0]
[63:0]
[63:0]
[3:0]
1
1
[<n>*2 – 1:0]
[<n>*2 – 1:0]
[<n>*2 – 1:0]
(Note 1)
Width
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10–3