IP-NIOS Altera, IP-NIOS Datasheet

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... Nios II Processor Reference Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com NII5V1-10.1 Nios II Processor Reference Document last updated for Altera Complete Design Suite version: Document publication date: Handbook 10.1 December 2010 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Getting Started with the Nios II Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Customizing Nios II Processor Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Configurable Soft-Core Processor Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Configurable Soft-Core Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Flexible Peripheral Set and Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Standard Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Custom Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Custom Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Automated System Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 OpenCore Plus Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1– ...

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... Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 The status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12 The estatus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14 The bstatus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The ienable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The ipending Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The cpuid Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The exception Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The pteaddr Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 The tlbacc Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17 The tlbmisc Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18 ...

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... Handling Nested Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–48 Nested Exceptions with the Internal Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49 Nested Exceptions with an External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49 Handling Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51 Returning From Interrupt and Instruction-Related Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51 Return Address Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–52 December 2010 Altera Corporation v Nios II Processor Reference Handbook ...

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... Masking and Disabling Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–52 Disabling Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–52 Masking Interrupts with an External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–52 Masking Interrupts with the Internal Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–53 Memory and Peripheral Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–53 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–53 Virtual Address Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–54 Instruction Set Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–55 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–55 Arithmetic and Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3– ...

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... External Interrupt Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13 JTAG Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14 Nios II/s Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 Multiply and Divide Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15 Shift and Rotate Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 Instruction and Data Master Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17 Tightly-Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5– ...

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... Procedure Linkage Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19 Linux Program Interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20 Linux Initialization and Termination Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Linux Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 System Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Userspace Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Atomic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Processor Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Nios II Processor Reference Handbook Contents December 2010 Altera Corporation ...

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... Assembler Pseudo-Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4 Assembler Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–104 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–104 Additional Information How to Find Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 December 2010 Altera Corporation ix Nios II Processor Reference Handbook ...

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... Nios II Processor Reference Handbook Contents December 2010 Altera Corporation ...

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... Part Number: NII51018-10.1.0 Chapter 7. Application Binary Interface Revised: Part Number: NII51016-10.1.0 Chapter 8. Instruction Set Reference Revised: Part Number: NII51017-10.1.0 December 2010 Altera Corporation December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 Chapter Revision Dates ...

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... Nios II Processor Reference Handbook Chapter Revision Dates December 2010 Altera Corporation ...

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... Chapter 3, Programming Model Chapter 4, Instantiating the Nios II Processor in SOPC Builder ■ f For information about the revision history for chapters in this section, refer to “Document Revision History” in each individual chapter. December 2010 Altera Corporation Section I. Nios II Processor Design ® II processor. Nios II Processor Reference Handbook ...

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... I–2 Nios II Processor Reference Handbook Section I: Nios II Processor Design December 2010 Altera Corporation ...

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... Introduction This handbook is the primary reference for the Nios processors. The handbook describes the Nios II processor from a high-level conceptual description to the low-level details of implementation. The chapters in this handbook define the Nios II processor architecture, the programming model, the instruction set, and more. ...

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... A Nios II processor system is equivalent to a microcontroller or “computer on a chip” that includes a processor and a combination of peripherals and memory on a single chip. A Nios II processor system consists of a Nios II processor core, a set of on-chip peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a single Altera device. Like a microcontroller family, all Nios II processor systems use a consistent instruction set and programming model ...

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... Because the pins and logic resources in Altera devices are programmable, many customizations are possible: You can rearrange the pins on the chip to simplify the board design. For example, ■ you can move address and data pins for external SDRAM memory to any side of the chip to shorten board traces ...

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... You can use extra pins and logic resources on the chip for functions unrelated to the processor. Extra resources can provide a few extra gates and registers as glue logic for the board design; or extra resources can implement entire systems. For example, a Nios II processor system consumes only large Altera FPGA, leaving the rest of the chip’ ...

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... You can also create custom peripherals and integrate them in Nios II processor systems. For performance-critical systems that spend most CPU cycles executing a specific section of code common technique to create a custom peripheral that implements the same function in hardware. This approach offers a double performance benefit: the hardware implementation is faster than software; and the processor is free to perform other functions in parallel while the custom peripheral operates on data ...

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... Maintenance release. November 2006 6.1.0 Maintenance release. Added single precision floating-point and integration with SignalTap ■ features list. May 2006 6.0.0 Updated performance to 250 DMIPS. ■ October 2005 5.1.0 Maintenance release. May 2005 5.0.0 Maintenance release. Nios II Processor Reference Handbook AN 320: OpenCore Plus Evaluation ...

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... Chapter 1: Introduction Document Revision History Table 1–1. Document Revision History (Part Date Version September 2004 1.1 Maintenance release. May 2004 1.0 Initial release. December 2010 Altera Corporation Changes Nios II Processor Reference Handbook 1–7 ...

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... Nios II Processor Reference Handbook Chapter 1: Introduction Document Revision History December 2010 Altera Corporation ...

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... Nios II instruction set and supports the functional units described in this document. The processor core does not include peripherals or the connection logic to the outside world. It includes only the circuits required to implement the Nios II architecture. ...

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... Optional Module Module chapter of the Nios II Processor Reference Handbook. Each Chapter 2: Processor Architecture Processor Implementation Tightly Coupled Instruction Memory Tightly Coupled Instruction Memory Instruction Bus Unit Data Bus Tightly Coupled Data Memory Data Tightly Coupled Data Memory December 2010 Altera Corporation ...

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... Inclusion or exclusion of a feature—For example, to reduce cost, you can choose to ■ omit the JTAG debug module. This decision conserves on-chip logic and memory resources, but it eliminates the ability to use a software debugger to debug applications. ■ ...

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... The ALU supports the data operations shown in Table 2–1. Operations Supported by the Nios II ALU Category Arithmetic The ALU supports addition, subtraction, multiplication, and division on signed and unsigned operands. The ALU supports the equal, not-equal, greater-than-or-equal, and less-than relational operations (==, Relational != >=, <) on signed and unsigned operands. ...

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... The Nios II Embedded Design Suite (EDS) provides software implementations of primitive floating-point operations other than addition, subtraction, multiplication, and division. This includes operations such as floating-point conversions and comparisons. The software implementations of these primitives are 100% compliant with IEEE 754-1985. December 2010 Altera Corporation ...

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... Nios II compiler compiles your code to use the custom instructions for floating-point operations, including addition, subtraction, multiplication, division and the newlib math library. Software Development Considerations The best choice for your hardware design depends on a balance among floating-point usage, hardware resource usage, and performance ...

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... With the GCC 4 compiler toolchain, precompiled libraries are compiled with double-precision floating-point constants. The behavior of precompiled floating-point library functions such as sin() and cos() is unaffected by the presence of the floating-point custom instructions. December 2010 Altera Corporation Floating-Point Custom Instructions Precision Present? No ...

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... This is an optional, local reset signal that causes the processor to reset without affecting other components in the Nios II system. The processor finishes executing any instructions in the pipeline, and then enters the reset state. This process can take several clock cycles sure to continue asserting the cpu_resetrequest signal ...

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... Earlier versions have an implementation of the eret instruction that is incompatible with shadow register sets. f For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the Embedded Peripherals IP User Processing” in the Handbook. Internal Interrupt Controller The Nios II architecture supports 32 internal hardware interrupts. The processor core has 32 level-sensitive interrupt request (IRQ) inputs, irq0 through irq31, providing a unique input for each interrupt source ...

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... Table 2–5. Interrupt Vector Custom Instruction ALT_CI_EXCEPTION_VECTOR_N if (ipending == 0) | (estatus.PIE == 0) then rC ← negative value Operation: else rC ← 8 × bit # of the least-significant 1 bit of the ipending register (ctl4) Assembler Syntax: custom ALT_CI_EXCEPTION_VECTOR_N, rC, r0, r0 custom ALT_CI_EXCEPTION_VECTOR_N, et, r0, r0 Example: blt et, r0, not_irq The interrupt vector custom instruction accelerates interrupt vector dispatch ...

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... The flexible nature of the Nios II memory and I/O organization are the most notable difference between Nios II processor systems and traditional microcontrollers. Because Nios II processor systems are configurable, the memories and peripherals vary from system to system result, the memory and I/O organization varies from system to system ...

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... The Nios II architecture supports separate instruction and data buses, classifying Harvard architecture. Both the instruction and data buses are implemented as Avalon-MM master ports that adhere to the Avalon-MM interface specification. The data master port connects to both memory and peripheral components, while the instruction master port connects only to memory components. f ...

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... Memory and Peripheral Access The Nios II architecture provides memory-mapped I/O access. Both data memory and peripherals are mapped into the address space of the data master port. The Nios II architecture is little endian. Words and halfwords are stored in memory with the more-significant bytes at higher addresses. ...

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... Nios II processor system might present a single, shared instruction/data bus to the outside world. The outside view of the Nios II processor system depends on the memory and peripherals in the system and the structure of the system interconnect fabric. The data and instruction master ports never cause a gridlock condition in which one port starves the other ...

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... Optimal cache configuration is application specific, although you can make decisions that are effective across a range of applications. For example Nios II processor system includes only fast, on-chip memory (i.e., it never accesses slow, off-chip memory), an instruction or data cache is unlikely to offer any performance gain. As another example, if the critical loop of a program is 2 kilobytes (KB), but the size of the instruction cache is 1 KB, an instruction cache does not improve execution speed ...

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... Memory with the Nios II Processor Address Map The address map for memories and peripherals in a Nios II processor system is design dependent. You specify the address map at system generation time. There are three addresses that are part of the processor and deserve special mention: ■ ...

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... Amount of region memory defined by size or upper address limit ■ Read and write access permissions for data regions ■ Execute access permissions for instruction regions Overlapping regions ■ December 2010 Altera Corporation Programming Model chapter of the Nios II Processor Nios II Processor Reference Handbook 2–17 ...

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... MPU or MMU, but cannot include both an MPU and MMU on the same Nios II processor core. JTAG Debug Module The Nios II architecture supports a JTAG debug module that provides on-chip emulation features to control the processor remotely from a host PC. PC-based software debugging tools communicate with the JTAG debug module and provide facilities, such as the following features: ■ ...

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... The following sections describe the capabilities of the Nios II JTAG debug module hardware. The usage of all hardware features is dependent on host software, such as the Nios II Software Build Tools for Eclipse, which manages the connection to the target processor and controls the debug process. JTAG Target Connection The JTAG target connection provides the ability to connect to the processor through the standard JTAG pins on the Altera FPGA ...

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... Trigger on a range of address values, data values, or both. Refer Data to “Triggering on Ranges of Values” on page Description Halt execution and transfer control to the JTAG debug module. Assert a trigger signal output. This trigger output can be used, for example, to trigger an external logic analyzer. Turn on trace collection. ...

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... Certain trace features require additional licensing or debug tools from third-party debug providers. For example, an on-chip trace buffer is a standard feature of the Nios II processor, but using an off-chip trace buffer requires additional debug software and hardware provided by First Silicon Solutions (FS2) or Lauterbach GmbH ...

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... Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor chapter of the Nios II Processor Reference chapter of the Nios II Processor Reference Handbook Embedded Peripherals IP User Guide page on the Altera website Changes Chapter 2: Processor Architecture Referenced Documents December 2010 Altera Corporation ...

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... Table 2–8. Document Revision History (Part Date Version Expanded floating-point instructions information. ■ November 2008 8.1.0 Updated description of optional cpu_resetrequest and cpu_resettaken signals. ■ Added description of optional debugreq and debugack signals. ■ May 2008 8.0.0 Added MMU and MPU sections. October 2007 7 ...

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... Nios II Processor Reference Handbook Chapter 2: Processor Architecture Document Revision History December 2010 Altera Corporation ...

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... While reading, be aware that all sections might not apply to you. For example, if you are using a minimal system runtime environment, you can skip the sections covering operating modes, the MMU, the MPU, or the control registers exclusively used by the MMU and MPU ...

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... Supervisor mode ■ User mode The following sections define the modes, their relationship to your system software and application code, and their relationship to the Nios II MMU and Nios II MPU. Refer to “Memory Management Unit” on page 3–3 Nios II MMU. Refer to about the Nios II MPU. ...

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... MMU-based Nios II processor. Do not include an MMU in your Nios II system unless your operating system requires it. 1 The Altera HAL and HAL-based real-time operating systems do not support the MMU. If your system needs memory protection, but not virtual memory management, refer to “ ...

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... Nios II Processor Reference Handbook Used By Memory Access Operating Bypasses TLB system Operating Bypasses TLB system Operating Uses TLB system Chapter 3: Programming Model Memory Management Unit Page Offset User Mode Default Data Access Cacheability No Disabled No Enabled No Set by TLB December 2010 Altera Corporation 0 ...

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... Note to Table 3–2: (1) Supervisor-only partition Each partition has a specific size, purpose, and relationship to the TLB: ■ The 512-megabyte (MB) I/O partition provides access to peripherals. The 512-MB kernel partition provides space for the operating system kernel. ■ The 1-GB kernel MMU partition is used by the TLB miss handler and kernel ■ ...

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... A TLB functions as a cache for the operating system’s page table. In Nios II processors with an MMU, one main TLB is shared by instruction and data accesses. The TLB is stored in on-chip RAM and handles translations for instruction fetches and instructions that perform data accesses. The TLB is organized as an n-way set-associative cache. The software specifies the way (set) when loading a new entry ...

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... G is the global flag. When the PID is ignored in the TLB lookup. Table 3–4 describes the data portion of a TLB entry. Description PFN is the physical frame number field. This field specifies the upper bits of the physical address. The size of this field depends on the range of physical addresses present in the system ...

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... Region size or upper address limit ■ ■ Access permissions ■ Default cacheability (data regions only) Nios II Processor Reference Handbook “Memory Management Unit” on page Chapter 3: Programming Model Memory Protection Unit Example 3–2. for details on TLB exceptions. 3–3. December 2010 Altera Corporation ...

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... Base Address The base address specifies the lowest address of the region. The base address is aligned on a region-sized boundary. For example region must have a base address that is a multiple of 4 KB. If the base address is not properly aligned, the behavior is undefined. Region Type Each region is identified as either an instruction region or a data region ...

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... Nios II Processor Reference Handbook for more information on cache bypass. for more information. Table 3–5. Some registers have names recognized by the Function Register r16 r17 r18 r19 Chapter 3: Programming Model Registers Name Function Callee-saved register Callee-saved register Callee-saved register Callee-saved register December 2010 Altera Corporation ...

Page 57

... The Nios II architecture supports control registers. the defined control registers. All nonreserved control registers have names recognized by the assembler. Table 3–6. Control Register Names and Bits (Part Register 0 status 1 estatus 2 bstatus 3 ienable 4 ipending 5 cpuid 6 Reserved 7 exception December 2010 Altera Corporation Function Register r20 r21 r22 r23 ...

Page 58

... Reserved Table 3–8 gives details of the fields defined in the status register. Table 3–8. status Control Register Field Descriptions (Part Bit RSIE is the register set interrupt-enable bit. When set to 1, this bit allows the processor to service external interrupts requesting the register set that RSIE is currently in use ...

Page 59

... Chapter 3: Programming Model Registers Table 3–8. status Control Register Field Descriptions (Part Bit PRS is the previous register set field. The processor copies the CRS field to the PRS field upon one of the following events processor with no MMU, on any exception ■ processor with an MMU, on one of the following: ■ ...

Page 60

... Table 3–8. status Control Register Field Descriptions (Part Bit PIE is the processor interrupt-enable bit. When PIE = 0, internal and maskable external interrupts and noninterrupt exceptions are ignored. When PIE = 1, internal and maskable external interrupts can be taken, PIE depending on the status of the interrupt controller. Noninterrupt exceptions are unaffected by PIE ...

Page 61

... When the internal interrupt controller is not implemented, the value of the ienable register is always 0. The ipending Register The value of the ipending register indicates the value of the interrupt signals driven into the processor. A value of one in bit n means that the corresponding irqn input is asserted. Writing a value to the ipending register has no effect. ...

Page 62

... To see how to control the extra exception information option, refer to the the Nios II Processor in SOPC Builder Table 3–11 shows the layout of the exception register. Table 3–11. exception Control Register Field Descriptions Field CAUSE is written by the Nios II processor when certain exceptions occur. CAUSE contains a code for the highest-priority exception occurring at the time ...

Page 63

... Issuing a rdctl instruction to the tlbacc register returns the value of the tlbacc register. The tlbacc register is written by hardware when software triggers a TLB read operation (that is, when wrctl sets tlbmisc.RD to one). Table 3–16. tlbacc Control Register Field Descriptions Field IG is ignored by hardware and available to hold operating system IG specific information ...

Page 64

... This field size is variable. Unused upper bits must be written as zero. Table 3–18 gives details of the fields defined in the tlbmisc register. Table 3–18. tlbmisc Control Register Field Descriptions Field The WAY field controls the mapping from the VPN to a particular TLB WAY entry ...

Page 65

... TLB has priority over the value written by the wrctl instruction. The size of the PID field is configured in SOPC Builder at system generation, and can be from bits. If system software defines a process identifier smaller than the PID field, unused upper bits must be written as zero. December 2010 Altera Corporation 3–19 Nios II Processor Reference Handbook ...

Page 66

... To see how to control the extra exception information option, refer to the the Nios II Processor in SOPC Builder Nios II Processor Reference Handbook Chapter 3: Programming Model for more information on these exceptions. chapter of the Nios II Processor Reference Handbook. December 2010 Altera Corporation Registers Instantiating ...

Page 67

... Table 3–20 gives details of the fields defined in the badaddr register. Table 3–20. badaddr Control Register Field Descriptions Field BADDR contains the byte instruction address or data address associated with an exception when certain exceptions occur. The BADDR Address column of Table 3–33 on page 3–32 exceptions write the BADDR field ...

Page 68

... The BASE field specifies the base address of an MPU region. The 25-bit BASE field corresponds to bits 6 through 30 of the base address, making the base address always a multiple of 64 bytes. If the minimum region size set in SOPC Builder at generation time is larger than 64 bytes, unused low-order bits of the BASE field must be written as zero and are read as zero ...

Page 69

... This field size is variable. Unused upper bits and unused lower bits must be written as zero. Table 3–27 gives details of the fields defined in the mpuacc register. Table 3–27. mpuacc Control Register Field Descriptions (Part Field (1) MASK specifies the size of the region. MASK (1) LIMIT specifies the upper address limit of the region ...

Page 70

... Table 3–27. mpuacc Control Register Field Descriptions (Part Field RD is the read region flag. When wrctl instructions to the RD mpuacc register perform a read operation the write region flag. When wrctl instructions to the WR mpuacc register perform a write operation. Note to Table 3–27: (1) The MASK and LIMIT fields are mutually exclusive. Refer to The following sections provide further details of the mpuacc fields ...

Page 71

... You can override the default cacheability and force an address to noncacheable with an ldio or stio instruction. 1 The bit 31 cache bypass feature is supported when the MPU is present. Refer to “Cache Memory” on page 3–53 December 2010 Altera Corporation MASK Encoding 0x1E00000 0x1C00000 0x1800000 ...

Page 72

... The WR flag always returns Chapter 3: Programming Model Registers Table 3–29 shows possible Table 3–30 shows possible values User Permissions None None Execute User Permissions None None Read None Read Read/Write “MPU Region Read “MPU Region Read December 2010 Altera Corporation ...

Page 73

... Reserved Table 3–32 gives details of the fields defined in the sstatus register. Table 3–32. sstatus Control Register Field Descriptions (Part Bit SRS is the switched register set bit. The processor sets SRS to 1 when an external interrupt occurs, if the interrupt required the processor to SRS switch to a different register set ...

Page 74

... Table 3–32. sstatus Control Register Field Descriptions (Part Bit CRS PIE Note to Table 3–32: (1) Refer to Table 3–8 on page 3–12. (2) If the EIC interface and shadow register sets are not present SRS always reads as 0, and the processor behaves accordingly. The sstatus register is present in the Nios II core if both the EIC interface and shadow register sets are implemented ...

Page 75

... Execute a wrctl instruction to the mpuacc register with the mpuacc.WR field set to one and the mpuacc.RD field cleared to zero. The MPU region write operation sets the values for mpubase.BASE, mpuacc.MASK or mpuacc.LIMIT, mpuacc.C, and mpuacc.PERM as the new attributes for the MPU region. December 2010 Altera Corporation 3–29 Nios II Processor Reference Handbook ...

Page 76

... Normally, a wrctl instruction flushes the pipeline to guarantee that any side effects of writing control registers take effect immediately after the wrctl instruction completes execution. However, wrctl instructions to the mpubase and mpuacc control registers do not automatically flush the pipeline. Instead, system software is responsible for flushing the pipeline as needed (either by using a flushp instruction or a wrctl instruction to a register that does flush the pipeline) ...

Page 77

... Each of the Nios II exceptions falls into one of the following categories: Reset exception—Occurs when the Nios II processor is reset. Control is transferred ■ to the reset address you specify in the Nios II processor IP core setup parameters. ■ Break exception—Occurs when the JTAG debug module requests control. Control is transferred to the break address you specify in the Nios II processor IP core setup parameters ...

Page 78

... Chapter 3: Programming Model Exception Processing Vector Reset Break Reset General exception Requested handler address (3) Requested handler address (3) General exception Fast TLB Miss exception General exception General exception General exception General exception General exception General exception General exception Break December 2010 Altera Corporation ...

Page 79

... It is possible for any instruction fetch to cause this exception. (2) Refer to Table 3–5 on page 3–10 for descriptions of the ea and ba registers. (3) For a description of the requested handler address, refer to Exception Latency Exception latency specifies how quickly the system can respond to an exception. Exception latency depends on the type of exception, the software and hardware configuration, and the processor state ...

Page 80

... Instruction and data memory. ■ ■ Cache memory, except for the instruction cache line associated with the reset vector. ■ Peripherals. Refer to the appropriate peripheral data sheet or specification for reset conditions. Custom instruction logic. Refer to the ■ conditions. ■ Nios II C-to-hardware (C2H) acceleration compiler logic. ...

Page 81

... Interrupt Exceptions A peripheral device can request an interrupt by asserting an interrupt request (IRQ) signal. IRQs interface to the Nios II processor through an interrupt controller. You can configure the Nios II processor with either of the following interrupt controller ...

Page 82

... Mode” The Nios II processor EIC interface connects to a single EIC, but an EIC can support a daisy-chained configuration daisy-chained configuration, multiple EICs can monitor and prioritize interrupts. The EIC directly connected to the processor presents the processor with the highest-priority interrupt from all EICs in the daisy chain ...

Page 83

... The method of assigning register sets to interrupts depends on the specific EIC implementation. Register set assignments can be software-configurable. Multiple interrupts can be configured to share a register set. In this case, the interrupt handlers must be written avoid register corruption. For example, one of the following conditions must be true: ■ ...

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... The value of the ipending control register shows which interrupt requests (IRQ) are pending. By peripheral design, an IRQ bit is guaranteed to remain asserted until the processor explicitly responds to the peripheral. between ipending, ienable, PIE, and the generation of an interrupt. 1 ...

Page 85

... If the instruction is not implemented in hardware, control is passed to an exception routine that might choose to emulate the instruction in software. For more information, refer to Unimplemented Instructions” on page December 2010 Altera Corporation “Exception Processing Flow” 3–34. 3–60. ...

Page 86

... Nios II Processor Reference Handbook Instantiating the Nios II Processor in SOPC chapter of the Nios II Processor Reference Handbook to see the Nios II Core Implementation Details “Operating Modes” on page 3–1 Table 3–2 on page Chapter 3: Programming Model Exception Processing for more information. 3–4. December 2010 Altera Corporation ...

Page 87

... Builder chapter of the Nios II Processor Reference Handbook. A data address is considered misaligned if the byte address is not a multiple of the width of the load or store instruction data width (four bytes for word, two bytes for half-word). Byte load and store instructions are always aligned so never take a misaligned address exception ...

Page 88

... TLB permission violation (execute)—Any instruction fetch can cause this exception. ■ TLB permission violation (read)—Any load instruction can cause this exception. TLB permission violation (write)—Any store instruction can cause this exception. ■ Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing December 2010 Altera Corporation ...

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... For a detailed discussion of writing programs to take advantage of exception and interrupt handling, refer to the Developer’s Handbook. December 2010 Altera Corporation “Processing a Break” on page Exception Handling chapter of the Nios II Software Nios II Processor Reference Handbook 3–43 ...

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... Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing chapter of the Nios II Processor Reference December 2010 Altera Corporation ...

Page 91

... Interrupts can be re-enabled by writing one to the PIE bit, thereby allowing the current ISR to be interrupted. Typically, the exception routine adjusts ienable so that IRQs of equal or lower priority are disabled before re-enabling interrupts. Refer to “Handling Nested Exceptions” on page 3–48 December 2010 Altera Corporation RNMI == 0 status.PIE == 1 RIL <= RIL > ...

Page 92

... Exception Processing status.EH==0 TLB Miss No TLB Miss (4) TLB No TLB Permission Permission Violation Violation (4) VPN (6) No change No change Fast TLB exception General exception vector vector (3) (9) No change (7) status return address (14) (15) (16) (17) 0 (19) 1 (20) No change No change No change No change No change December 2010 Altera Corporation ...

Page 93

... To determine the cause of an exception, simply read the cause of the exception from exception.CAUSE and then transfer control to the appropriate exception routine. 1 Extra exception information is always enabled in Nios II systems containing an MMU or MPU. December 2010 Altera Corporation “The exception Register” on page “The badaddr Register” on page for more information. 3–47 3– ...

Page 94

... Example 3–3. Determining Exception Cause Without Extra Exception Information /* With an internal interrupt controller, check for interrupt exceptions. With an external interrupt controller, ipending is always 0, and this check can be omitted (estatus.PIE == 1 and ipending != 0) { handle interrupt /* Decode exception from instruction */ /* Note: Because the exception register is included with the MMU and */ ...

Page 95

... Each interrupt is assigned to a dedicated shadow register set ■ All interrupts with the same RIL are assigned to dedicated shadow register sets. December 2010 Altera Corporation 3–43. For details about unimplemented instructions, refer chapter of the Nios II Processor Reference Handbook. For “Instruction-Related Exceptions” on Nios II Processor Reference Handbook 3– ...

Page 96

... Noninterrupt exception handlers must always save and restore the register contents, because they run in the normal register set. Multiple interrupts can share a register set, with some loss of performance. There are two techniques for sharing register sets: Set status.RSIE to 0. When an ISR is running in a given register set, the processor ■ ...

Page 97

... It is not necessary to save and restore the exception temporary (et or r24) register. When executing the eret instruction, the processor performs the following tasks: December 2010 Altera Corporation 3–49. “Nested Exceptions with an External Nios II Processor Reference Handbook ...

Page 98

... Masking Interrupts with an External Interrupt Controller Masking Individual Interrupts Typical EIC implementations allow system software to mask individual interrupts. The method of masking individual interrupts is implementation-specific. Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing December 2010 Altera Corporation ...

Page 99

... Processor Reference Handbook. Peripherals, data memory, and program memory are mapped into the same address space. The locations of memory and peripherals within the address space are determined at system generation time. Reading or writing to an address that does not map to a memory or peripheral produces an undefined result. ...

Page 100

... Code written for a processor core with cache memory behaves correctly on a processor core without cache memory. The reverse is not true necessary for a program to work properly on multiple Nios II processor core implementations, the program must behave as if the instruction and data caches exist. In systems without cache memory, the cache management instructions perform no operation, and their effects are benign ...

Page 101

... Memory accesses can be cached or buffered to improve performance. To transfer data to I/O peripherals, ldhu use the “io” versions of the instructions, described below. sth ...

Page 102

... These instructions are immediate versions of the add, sub, and mul instructions. The instruction word subi includes a 16-bit signed value. muli These instructions provide access to the upper 32 bits of a 32x32 multiplication operation. Choose the mulxss appropriate instruction depending on whether the operands should be treated as signed or unsigned mulxuu values ...

Page 103

... December 2010 Altera Corporation Table Description Description Nios II Processor Reference Handbook 3–57 3–42. Table 3–43. ...

Page 104

... Nios II Processor Reference Handbook Table 3–44. These instructions do not have delay slots. Description Table 3–45. The conditional branches support the following Description “Comparison Instructions” on page 3–57 Chapter 3: Programming Model Instruction Set Categories for a description of the December 2010 Altera Corporation ...

Page 105

... These instructions are used to manage the data and instruction cache memories. initd initda initi This instruction flushes all prefetched instructions from the pipeline. This is necessary before jumping to flushp recently-modified instruction memory. This instruction ensures that all previously-issued operations have completed before allowing execution of sync subsequent load and store operations ...

Page 106

... Nios II Processor Reference Handbook chapter of the Nios II Processor chapter of the Nios II Processor Reference chapter of the Nios II Software Developer’s Handbook chapter of the Nios II Software Developer’s Embedded Peripherals IP User Guide Chapter 3: Programming Model Referenced Documents December 2010 Altera Corporation ...

Page 107

... Maintenance release. Added details for new control register ctl5. ■ September 2004 1.1 Updated details of debug and break processing to reflect new behavior of the break ■ instruction. May 2004 1.0 Initial release. December 2010 Altera Corporation Changes Nios II Processor Reference Handbook 3–61 ...

Page 108

... Nios II Processor Reference Handbook Chapter 3: Programming Model Document Revision History December 2010 Altera Corporation ...

Page 109

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 110

... The main purpose of the Core Nios II page is to select the processor core. The core you select on this page affects other options available on this and other pages. Altera offers the following Nios II cores: ■ Nios II/f—The Nios II/f “fast” core is designed for fast performance result, this core presents the most configuration options allowing you to fine-tune the processor for performance ...

Page 111

... The Nios II/s and Nios II/f cores offer hardware multiply and divide options. You can choose the best option to balance embedded multiplier usage, logic element (LE) usage, and performance. The Hardware Multiply setting for each core provides a subset of the options in the following list: DSP Block—Include DSP block multipliers in the arithmetic logic unit (ALU). ...

Page 112

... Do not include an MMU in your Nios II system unless your operating system requires it. The MMU is only useful with software that takes advantage of it. Many Nios II systems involve simpler system software, such as Altera Such software is unlikely to function correctly with an MMU-based Nios II processor. Fast TLB Miss Exception Vector The fast TLB miss exception vector is a special exception vector used exclusively by the MMU to handle TLB miss exceptions ...

Page 113

... DRAM, and disable bursts when instructions are stored in SRAM. Bursting to DRAM typically improves memory bandwidth, but might consume additional FPGA resources. Be aware that when bursts are enabled, accesses to December 2010 Altera Corporation Programming Model chapter of the Nios II Programming Model chapter of the Nios II Figure 4– ...

Page 114

... For example, with a 32-byte cache line, transferring control to address 8 results in a burst with the following address sequence: 8, 12, 16, 20, 24, 28 Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder . MAX Caches and Memory Interfaces Page December 2010 Altera Corporation ...

Page 115

... Omit data master port—If you set Data Cache to None, you can optionally ■ turn on Omit data master port to remove the Avalon-MM data master port from the Nios II processor. In this case, you must include a tightly-coupled data memory. December 2010 Altera Corporation 4–7 Nios II Processor Reference Handbook ...

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... Nios II processor in the SOPC Builder System Contents tab. You must connect each port to exactly one memory component in the system. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder . MAX Caches and Memory Interfaces Page December 2010 Altera Corporation ...

Page 117

... Nios II processor without resetting the entire SOPC Builder system. The signals are exported to the top level of your SOPC Builder system. f For further details on the reset signals, refer to the Nios II Processor Reference Handbook. December 2010 Altera Corporation shows the Advanced Features page. Processor Architecture 4–9 chapter of the ...

Page 118

... Misaligned memory access—Misaligned memory access detection is only available for the Nios II/f core. When Misaligned memory access is on, the processor checks for misaligned memory accesses. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder Advanced Features Page December 2010 Altera Corporation ...

Page 119

... Misaligned data address—Data addresses of load and store instructions are ■ checked for misalignment. A data address is considered misaligned if the byte address is not a multiple of the data width of the load or store instruction (4 bytes for word, 2 bytes for half-word). Byte load and store instructions are always aligned so never generate a misaligned data address exception. ...

Page 120

... Figure 4–4. MMU and MPU Settings Page in the Nios II Processor Parameter Editor Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder shows the MMU and MPU Settings page. MMU and MPU Settings Page Programming Model December 2010 Altera Corporation ...

Page 121

... The maximum region size is the size of the Nios II instruction and data addresses automatically determined when the Nios II system is generated in SOPC Builder. Maximum region size is based on the address range of slaves connected to the Nios II instruction and data masters. December 2010 Altera Corporation Programming Model chapter of the Nios II Processor chapter of the Nios II Processor Reference Handbook. ...

Page 122

... Data Trace processor in real time. On-Chip Trace Stores trace data in on-chip memory. Stores trace data in an external debug probe. Off-chip trace instantiates a PLL inside the Nios II Off-Chip Trace core. Off-chip trace requires a debug probe from First Silicon Solutions (FS2) or Lauterbach GmbH. ...

Page 123

... Figure 4–5. JTAG Debug Module Page in the Nios II Processor Parameter Editor Table 4– detailed list of the characteristics of each debug level. Different levels consume different amounts of on-chip resources. Certain Nios II cores have restricted debug options, and certain options require debug tools provided by First Silicon Solutions (FS2) or Lauterbach GmbH. ...

Page 124

... Advanced Debug Settings Debug levels 3 and 4 support trace data collection into an on-chip memory buffer. You can set the on-chip trace buffer size to sizes from 128 to 64K trace frames, using OCI Onchip Trace. Larger buffer sizes consume more on-chip M4K RAM blocks. Every M4K RAM block can store up to 128 trace frames ...

Page 125

... To display custom instructions in the table of active components on the SOPC Builder System Contents tab, click Filter in the lower right of the System Contents tab, and turn on Nios Custom Instruction. December 2010 Altera Corporation Processor Architecture chapter of the Nios II Processor Reference Handbook 4–17 ...

Page 126

... For full details on the topic of custom instructions, including working example designs, refer to the Instruction User The following sections describe the default custom instructions Altera provides. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder Guide ...

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... If the target device includes on-chip multiplier blocks, the floating-point custom instructions incorporate them as needed. If there are no on-chip multiplier blocks, the floating-point custom instructions are entirely based on general-purpose logic elements. ...

Page 128

... To add the floating-point custom instructions to the Nios II processor, select Floating Point Hardware from the list, and click Add. By default, SOPC Builder includes floating-point addition, subtraction, and multiplication, but omits the more resource intensive floating-point division. The Floating Point Hardware wizard, shown in Figure 4– ...

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... The Quartus Manager or SOPC Builder that contains information about a generated IP core. You are prompted to add this .qip file to the current project at the time of Quartus II file generation. In most cases, the .qip file contains all of the necessary assignments and information required to process the core or system in the Quartus II compiler. ...

Page 130

... New details in “Caches and Tightly-Coupled Memory” section. ■ Updates to reflect new GUI options in Nios II processor version 1.1. ■ September 2004 1.1 New details in section “Multiply and Divide Settings.” ■ May 2004 1.0 Initial release. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder Changes “ ...

Page 131

... Chapter 7, Application Binary Interface Chapter 8, Instruction Set Reference ■ f For information about the revision history for chapters in this section, refer to “Document Revision History” in each individual chapter. December 2010 Altera Corporation Section II. Nios II Processor Implementation and Reference ® II processor. Nios II Processor Reference Handbook ...

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... II–2 Nios II Processor Reference Handbook Section II: Nios II Processor Implementation and Reference December 2010 Altera Corporation ...

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... Table 5–1. Nios II Processor Cores (Part Feature Objective DMIPS/MHz (1) Performance Max. DMIPS (2) Max. f (2) MAX Area Pipeline © 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. ...

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... Hardware Multiply Hardware Divide Arithmetic Logic Unit Shifter JTAG interface, run control, software breakpoints JTAG Debug Module Hardware Breakpoints Off-Chip Trace Buffer Memory Management Unit Memory Protection Unit Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details Core Nios II/e Nios II – ...

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... Multiply and shift performance depends on the hardware multiply option you use hardware multiply option is used, multiply operations are emulated in software, and shift operations require one cycle per bit. For details, refer to the arithmetic logic unit description for each core. Device Family Support ...

Page 136

... Table 5–2: (1) Device support levels are defined in Table 5–3 defines the device support level nomenclature used by Altera IP cores. Table 5–3. Altera IP Core Device Support Levels FPGA Device Families Preliminary support—The core is verified with preliminary timing models for this device family. The core meets all functional requirements, but might still be undergoing timing analysis for the device family ...

Page 137

... This option is available only on Altera FPGAs that have embedded multipliers. Logic Elements—Includes hardware multipliers built from logic element (LE) ■ resources. ■ None—Does not include multiply hardware. In this case, multiply operations are emulated in software. December 2010 Altera Corporation 5–5 Nios II Processor Reference Handbook ...

Page 138

... In the following code example, a multiply operation (with 1 instruction cycle and 2 result latency cycles) is followed immediately by an add operation that uses the result of the multiply. On the Nios II/f core, the addi instruction, like most ALU instructions, executes in a single cycle. However, in this code example, execution of the addi instruction is delayed by two additional cycles until the multiply operation completes ...

Page 139

... Shift and Rotate Performance The performance of shift operations depends on the hardware multiply option. When a hardware multiplier is present, the ALU achieves shift and rotate operations in one or two clock cycles. Otherwise, the ALU includes dedicated shift circuitry that achieves one-bit-per-cycle shift and rotate performance. Refer to page 5– ...

Page 140

... Write-allocate (i.e store instruction, a cache miss allocates the line for that address) Virtually-indexed, physically-tagged, when MMU present ■ Nios II Processor Reference Handbook shows the cache physical byte address fields for systems with line Chapter 5: Nios II Core Implementation Details Nios II/f Core offset offset December 2010 Altera Corporation 0 0 ...

Page 141

... When the data cache is enabled, you can enable bursting on the data master port. Consult the documentation for memory devices connected to the data master port to determine whether bursting can improve performance. December 2010 Altera Corporation Table 5–9 Ignore Tag Field Consider Tag Field ...

Page 142

... For details on the MMU architecture, refer to the Nios II Processor Reference Handbook. Micro Translation Lookaside Buffers The translation lookaside buffer (TLB) consists of one main TLB stored in on-chip RAM and two separate micro TLBs (μTLB) for instructions (μITLB) and data (μDTLB) stored in LE-based registers. ...

Page 143

... Data dependencies on long latency instructions (e.g., load, multiply, shift). Pipeline Stalls The pipeline is set up so that if a stage stalls, no new values enter that stage or any earlier stages. No “catching up” of pipeline stages is allowed, even if a pipeline stage is empty. Only the A-stage and D-stage are allowed to create stalls. ...

Page 144

... Late result instructions have two cycles placed between them and an instruction that uses their result. Instructions that flush the pipeline cause up to three instructions after them to be cancelled. This creates a three-cycle penalty and an execution time of four cycles. Instructions that require Avalon-MM transfers are stalled until any required Avalon-MM transfers (up to one write and one read) are completed ...

Page 145

... Shift/rotate (without hardware multiply present) All other instructions Note to Table 5–10: (1) Depends on the hardware multiply or divide option. Refer to (2) In the default Nios II/f configuration, these instructions require four clock cycles. If any of the following options are present, they require five clock cycles: MMU ■ ...

Page 146

... The Nios II MMU does not support the JTAG debug module trace. Nios II/s Core The Nios II/s standard core is designed for small core size. On-chip logic and memory resources are conserved at the expense of execution performance. The Nios II/s core uses approximately 20% less logic than the Nios II/f core, but execution performance also drops by roughly 40% ...

Page 147

... Logic Elements—Includes hardware multipliers built from logic element (LE) resources. None—Does not include multiply hardware. In this case, multiply operations are ■ emulated in software. The Nios II/s core also provides a hardware divide option that includes LE-based divide circuitry in the ALU. ...

Page 148

... Shift and Rotate Performance The performance of shift operations depends on the hardware multiply option. When a hardware multiplier is present, the ALU achieves shift and rotate operations in three or four clock cycles. Otherwise, the ALU includes dedicated shift circuitry that achieves one-bit-per-cycle shift and rotate performance. Refer to page 5– ...

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... Execution Pipeline This section provides an overview of the pipeline behavior for the benefit of performance-critical applications. Designers can use this information to minimize unnecessary processor stalling. Most application programmers never need to analyze the performance of individual instructions. ...

Page 150

... Data dependencies on long latency instructions (e.g., load, multiply, shift operations) Pipeline Stalls The pipeline is set up so that if a stage stalls, no new values enter that stage or any earlier stages. No “catching up” of pipeline stages is allowed, even if a pipeline stage is empty. Only the M-stage is allowed to create stalls. ...

Page 151

... Instruction Performance All instructions take one or more cycles to execute. Some instructions have other penalties associated with their execution. Instructions that flush the pipeline cause up to three instructions after them to be cancelled. This creates a three-cycle penalty and an execution time of four cycles. Instructions that require an Avalon-MM transfer are stalled until the transfer completes ...

Page 152

... Nios II/e Core The Nios II/e economy core is designed to achieve the smallest possible core size. Altera designed the Nios II/e core with a singular design goal: reduce resource utilization any way possible, while still maintaining compatibility with the Nios II instruction set architecture. Hardware resources are conserved at the expense of execution performance ...

Page 153

... For information regarding data cache bypass methods, refer to the Architecture chapter of the Nios II Processor Reference Handbook. Instruction Execution Stages This section provides an overview of the pipeline behavior as a means of estimating assembly execution time. Most application programmers never need to analyze the performance of individual instructions. Instruction Performance The Nios II/e core dispatches a single instruction at a time, and the processor waits for an instruction to complete before fetching and dispatching the next instruction ...

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... Corrected cycle counts for shift/rotate operations. Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook Embedded Peripherals IP User Guide Changes Referenced Documents December 2010 Altera Corporation ...

Page 155

... Chapter 5: Nios II Core Implementation Details Document Revision History Table 5–17. Document Revision History (Part Date Version December 2004 1.2 Updates to Multiply and Divide Performance section for Nios II/f and Nios II/s cores. September 2004 1.1 Updates for Nios II 1.01 release. May 2004 1.0 Initial release. ...

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... Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details Document Revision History December 2010 Altera Corporation ...

Page 157

... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 158

... Minor enhancements to the architecture: Added cpuid control register, ■ and updated the break instruction. Increased user control of multiply and shift hardware in the arithmetic ■ logic unit (ALU) for Nios II/s and Nios II/f cores. Minor bug fixes. ■ Minor bug fixes. ...

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... December 2010 10.0 July 2010 9.1 November 2009 9.0 March 2009 8.1 November 2008 December 2010 Altera Corporation Notes No changes. No changes. Added an optional MMU. ■ Added an optional MPU. ■ Added advanced exception checking to detect division errors, illegal ■ instructions, misaligned memory accesses, and provide extra exception information ...

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... Use embedded multiplier resources available in the target device family (previously available). (2) Use logic elements to implement multiply and shift hardware (new option). (3) Omit multiply hardware. Shift operations take one cycle per bit shifted; multiply operations are emulated in software (new option). Added cpuid control register. ...

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... December 2010 Altera Corporation Bug Fixes: ■ (1) When a store to memory is followed immediately in the pipeline by a load from the same memory location, and the memory location is held in the data cache, the load may return invalid data. This situation can occur in C code compiled with optimization off (-O0) ...

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... Use embedded multiplier resources available in the target device family (previously available). (2) Use logic elements to implement multiply and shift hardware (new option). (3) Omit multiply hardware. Shift operations take one cycle per bit shifted; multiply operations are emulated in software (new option). Added user-configurable option to include divide hardware in the ALU. Previously ■ ...

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... November 2006 6.0 May 2006 5.1 October 2005 5.0 May 2005 1.1 December 2004 1.01 September 2004 1.0 May 2004 December 2010 Altera Corporation Notes No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. Support for HardCopy devices (previous versions of the JTAG debug module did not support HardCopy devices) ...

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... Updates for Nios II cores version 5.1. May 2005 5.0.0 Updates for Nios II cores version 5.0. September 2004 1.1 Updates for Nios II cores version 1.1. May 2004 1.0 Initial release. Nios II Processor Reference Handbook Chapter 6: Nios II Processor Revision History Referenced Documents Changes December 2010 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Return value (most-significant 32 bits) v Register arguments (first 32 bits) v Register arguments (second 32 bits) v Register arguments (third 32 bits) v Register arguments (fourth 32 bits Caller-saved general-purpose registers Callee-saved general-purpose registers (2) v (3) Exception temporary Chapter 7: Application Binary Interface Memory Alignment Normal Usage December 2010 Altera Corporation ...

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... Stacks The stack grows downward (i.e. towards lower addresses). The stack pointer points to the last used slot. The frame pointer points to the saved frame pointer near the top of the stack frame. December 2010 Altera Corporation Used by Callee Compiler Saved ...

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... Allocated and freed by a() stack (i.e. the calling function) arguments Return address Saved frame pointer Frame pointer Other saved registers Space for stack Allocated and freed by b() temporaries (i.e. the current function) Space for outgoing stack arguments Stack pointer Stacks December 2010 Altera Corporation ...

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... Stack Frame for a Function with Variable Arguments Functions that take variable arguments (varargs) still have their first 16 bytes of arguments arriving in registers r4 through r7, just like other functions. December 2010 Altera Corporation Figure 7–2 depicts what the frame looks like after alloca() is Before ...

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... Frame pointer Other saved registers Allocated and freed by b() (i.e. the current function) Space for stack temporaries Space for outgoing stack arguments Stack pointer Figure 7–3. 7–2. A function prologue is required to save a Chapter 7: Application Binary Interface Stacks 7–3. December 2010 Altera Corporation ...

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... Arguments and Return Values This section discusses the details of passing arguments to functions and returning values from functions. December 2010 Altera Corporation shows a function prologue. /* make a 16-byte frame */ /* store the return address */ /* store the frame pointer*/ ...

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... In Example 7–2, if the result type is no larger than 8 bytes, b() returns its result in r2 and r3. Nios II Processor Reference Handbook Chapter 7: Application Binary Interface Arguments and Return Values “Stack Frame for a Function 7–5. December 2010 Altera Corporation ...

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... Nios II relocation type. The bit mask specifies where the address is found in the instruction. Table 7–4. Nios II Relocation Calculation (Part Name Value R_NIOS2_NONE 0 R_NIOS2_S16 1 R_NIOS2_U16 2 R_NIOS2_PCREL16 3 R_NIOS2_CALL26 4 December 2010 Altera Corporation Example 7–3 Example 7–2. Value ELFCLASS32 ELFDATA2LSB EM_ALTERA_NIOS2 == 113 Overflow Relocated Address check (1) R (2) n/a ...

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... Bit Mask Bit Shift M B 0x000007C0 6 0x07C00000 22 0x00000FC0 6 0x00003FC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0xFFFFFFFF 0 0x0000FFFF 0 0x000000FF 0 0x003FFFC0 6 n/a n/a n/a n/a 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 n/a n/a 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0xFFFFFFFF 0 0xFFFFFFFF 0 December 2010 Altera Corporation ...

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... GOT: The value of the Global Offset Table (GOT) pointer (Linux only) ■ G: The offset into the GOT for the GOT slot for symbol S (Linux only) ■ (3) Relocation support is provided for Linux systems. With the information in manipulating unsigned 32-bit integer, as follows << & & ~M )); where: ■ the relocated address, calculated as shown in ■ ...

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... R_NIOS2_PCREL_HA R_NIOS2_TLS_GD16 R_NIOS2_TLS_LDM16 R_NIOS2_TLS_LDO16 R_NIOS2_TLS_IE16 R_NIOS2_TLS_LE16 R_NIOS2_TLS_DTPREL R_NIOS2_GOTOFF Nios II Processor Reference Handbook Chapter 7: Application Binary Interface Table Table 7–6. Operator %got %call %gotoff_hiadj %gotoff_lo %hiadj %lo %tls_gd %tls_ldm %tls_ldo %tls_ie %tls_le %tls_ldo %gotoff ABI for Linux Systems 7–5. December 2010 Altera Corporation ...

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... Address the general dynamic model, a two-word GOT slot is allocated for x, as shown in Example 7–5. Example 7–5. GOT Slot for General Dynamic Model GOT[n] GOT[n+1] December 2010 Altera Corporation 7–19. shows the general dynamic model. # R_NIOS2_TLS_GD16 x # R_NIOS2_CALL26 __tls_get_addr R_NIOS2_TLS_DTPMOD x R_NIOS2_TLS_DTPREL x 7–13 ...

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... R_NIOS2_TLS_LDM16 x # R_NIOS2_CALL26 __tls_get_addr # R_NIOS2_TLS_LDO16 x # R_NIOS2_TLS_LDO16 x2 R_NIOS2_TLS_DTPMOD x 0 shows the initial exec model. # R_NIOS2_TLS_IE16 x R_NIOS2_TLS_TPREL x shows the local exec model. # R_NIOS2_TLS_LE16 x 7–11. # DW_OP_addr # R_NIOS2_TLS_DTPREL x # DW_OP_GNU_push_tls_address Chapter 7: Application Binary Interface ABI for Linux Systems December 2010 Altera Corporation ...

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... Linux systems r23 is a general-purpose, callee-saved register. The global pointer, r26 or gp, is globally fixed initialized in startup code and always valid on entry to a function. This method does not allow for multiple gp values, so gp-relative data references are only possible in the main application (that is, from position dependent code) ...

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... SIGSEGV SIGSEGV 7–21. Start Address High addresses × argc × argc Low addresses Chapter 7: Application Binary Interface ABI for Linux Systems Table 7–8 shows the Length Varies 4 bytes 8 bytes each 4 bytes 4 bytes each 4 bytes 4 bytes each 4 bytes December 2010 Altera Corporation ...

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... GOT entry is placed in the PLT GOT for lazy binding, as shown in For information about the PLT, refer to Example 7–15. GOT entry in PLT GOT ldw r3, %call(fun)(r22) callr r3 PLTGOT[n] December 2010 Altera Corporation # R_NIOS2_PCREL_HA _gp_got # R_NIOS2_PCREL_LO _gp_got - 4 # R_NIOS2_GOT16 R_NIOS2_GLOB_DAT x # R_NIOS2_GOT16 R_NIOS2_RELATIVE +x Example “ ...

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... GOT. The linker-defined symbol _gp_got points to the base address used for GOT-relative relocations. The value of _gp_got might vary between object files if the linker creates multiple GOT sections. Function Addresses Function addresses use the same SHN_UNDEF and st_value convention for PLT entries as in other architectures, such as x86_64 ...

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... The link editor arranges for the Nth PLT entry to point to the Nth branch, res_N – res_0 is four times the index into the .rela.plt section for the corresonding R_JUMP_SLOT relocation. December 2010 Altera Corporation Example 7–18. shows the PLT entry when the PLT GOT is close enough to the small shows the initial PLT entry. 7– ...

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... Linux Program Interpreter The program interpreter is /lib/ld.so.1. Nios II Processor Reference Handbook shows the initial PLT entry. Chapter 7: Application Binary Interface ABI for Linux Systems Example 7–23. December 2010 Altera Corporation ...

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... Applications must use those functions rather than the system call directly. Atomic operations may be added in a future processor extension. Processor Requirements Linux requires that a hardware multiplier be present. The full 64-bit multiplier (mulx instructions) is not required. Development Environment The following symbols are defined: ■ ...

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... November 2009 9.1.0 Maintenance release. March 2009 9.0.0 Backwards-compatible change to the eret instruction B field encoding. November 2008 8.1.0 Maintenance release. Frame pointer description updated. ■ May 2008 8.0.0 Relocation table added. ■ October 2007 7.2.0 Maintenance release. Added table of contents to Introduction section. ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 188

... A 26-bit immediate data field J-type instructions, such as call and jmpi, transfer execution anywhere within a 256-MB range. Table 8–3 shows the J-type instruction format. Table 8–3. J-Type Instruction Format Nios II Processor Reference Handbook OPX IMM26 Chapter 8: Instruction Set Reference Word Formats December 2010 Altera Corporation 0 0 ...

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... December 2010 Altera Corporation and Table 8–2. Most values of OP are encodings for I-type Instruction OP Instruction cmplti 0x20 cmpeqi 0x21 0x22 initda 0x23 ldbuio ori ...

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... IMMED addi, rB, r0, IMMED orhi rB, r0, %hiadj(label) addi, rB, r0, %lo(label) ori rB, r0, IMMED add r0, r0, r0 addi rB, rA, (-IMMED) Chapter 8: Instruction Set Reference Assembler Pseudo-Instructions OPX Instruction 0x3E 0x3F Equivalent Instruction December 2010 Altera Corporation ...

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... σ (X) X >> << & Y December 2010 Altera Corporation Table 8–4 lists the available macros. These macros return Description immed32 & 0xFFFF (immed32 >> 16) & 0xFFFF ((immed32 >> 16) & 0xFFFF) + ((immed32 >> 15) & 0x1) immed32 –_gp (1) Meaning X is written with Y The program counter (PC) is written with address X ...

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... The word located in data memory at byte address X An address label specified in the assembly file The value of rX treated as a signed number The value of rX treated as an unsigned number Chapter 8: Instruction Set Reference Instruction Set Reference Programming Model chapter December 2010 Altera Corporation ...

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... Assembler Syntax: add rC, rA, rB Example: add r6, r7, r8 Calculates the sum of rA and rB. Stores the result in rC. Used for both signed and unsigned Description: addition. Carry Detection (unsigned operands): Following an add operation, a carry out of the MSB can be detected by checking whether the Usage: unsigned sum is less than one of the unsigned operands ...

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... IMM16 Example: addi r6, r7, -100 Sign-extends the 16-bit immediate value and adds it to the value of rA. Stores the sum in rB. Description: Carry Detection (unsigned operands): Following an addi operation, a carry out of the MSB can be detected by checking whether the Usage: unsigned sum is less than one of the unsigned operands. The carry bit can be written to a register conditional branch can be taken based on the carry condition ...

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... Instruction Set Reference and rC ← rA & rB Operation: Assembler Syntax: and rC, rA, rB Example: and r6, r7, r8 Calculates the bitwise logical AND of rA and rB and stores the result in rC. Description: None Exceptions: R Instruction Type Register index of operand Register index of operand rB Instruction Fields Register index of operand rC ...

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... Operation: Assembler Syntax: andhi rB, rA, IMM16 Example: andhi r6, r7, 100 Calculates the bitwise logical AND of rA and (IMM16 : 0x0000) and stores the result in rB. Description: None Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: ...

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... IMM16) Operation: Assembler Syntax: andi rB, rA, IMM16 Example: andi r6, r7, 100 Calculates the bitwise logical AND of rA and (0x0000 : IMM16) and stores the result in rB. Description: None Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: ...

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... rB, then beq transfers program control to the instruction at label. In the instruction encoding, the offset given by IMM16 is treated as a signed number of bytes relative to the Description: instruction immediately following beq. The two least-significant bits of IMM16 are always zero, because instruction addresses must be word-aligned. ...

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... If (signed) rA >= (signed) rB, then bge transfers program control to the instruction at label. In the instruction encoding, the offset given by IMM16 is treated as a signed number of bytes Description: relative to the instruction immediately following bge. The two least-significant bits of IMM16 are always zero, because instruction addresses must be word-aligned. ...

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... If (unsigned) rA >= (unsigned) rB, then bgeu transfers program control to the instruction at label. In the instruction encoding, the offset given by IMM16 is treated as a signed number of Description: bytes relative to the instruction immediately following bgeu. The two least-significant bits of IMM16 are always zero, because instruction addresses must be word-aligned. ...