IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 53

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Figure 5–1. Interlaken PHY IP Core
December 2010 Altera Corporation
f
Fabric
FPGA
Interlaken is a high speed serial communication protocol for chip-to-chip packet
transfers. The Altera Interlaken PHY IP core implements
Specification, Rev
up to 10.3125 Gbps on Stratix V devices. The key advantage of Interlaken is its low
I/O count compared to earlier protocols such as SPI 4.2. Other key features include
flow control, low overhead framing, and extensive integrity checking. The Interlaken
physical coding sublayer (PCS) transmits and receives Avalon-ST data on its FPGA
fabric interface. It transmits and receives high speed differential serial data using the
PCML I/O standard.
PHY.
For more information about the Avalon-ST protocol, including timing diagrams, refer
to the
Interlaken operates on 64-bit data words which are striped round robin across the
lanes to reduce latency. Striping renders the interface independent of exact lane count.
The protocol accepts packets on 256 logical channels. Packets are split into small
bursts which can optionally be interleaved. The burst semantics include integrity
checking and per channel flow control.
The Interlaken PCS supports the following framing functions on a per lane basis:
■
■
■
■
■
■
Gearbox
Block synchronization
64b/67b encoding and decoding
Scrambling and descrambling
Lane-based CRC32
DC balancing
Avalon-ST
Tx and Rx
Avalon Interface
Interlaken PHY IP Core
PCS
1.2. It supports multiple instances, each with 1–24 lanes running at
64b/67b Encoding/Decoding
Scrambing/Descrambling
Block Synchronization
Figure 5–1
Specifications.
Lane-Based CRC32
DC Balancing
Framing:
Gearbox
illustrates the top-level modules of the Interlaken
5. Interlaken PHY IP Core
PMA
Serializer
Serializer
and CDR
De-
Altera Transceiver PHY IP Core User Guide
HSSI I/O
Interlaken Protocol
10.3125 Gbps
rx_serial_data
tx_serial_data
up to