IPR-XAUIPCS Altera, IPR-XAUIPCS Datasheet - Page 49

• Manufacturer Part Number: IPR-XAUIPCS
• Description: IP CORE Renewal Of IP-XAUIPCS
• Manufacturer: Altera

Specifications of IPR-XAUIPCS

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Stratix IV GT, Stratix V
• Features: 10Gbase-R PHY IP Core, Xaui PHY IP Core, Memory-Mapped (Avalon-Mm) Interface
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: XAUI PHY IP Core
Interfaces
Table 4–15. Optional Control and Status Signals—Hard IP Implementation, Stratix IV GX Devices (Part 1 of 2)
December 2010 Altera Corporation
rx_invpolarity[3:0]
rx_set_locktodata[3:0]
rx_is_lockedtodata[3:0]
rx_set_locktoref[3:0]
rx_is_lockedtoref[3:0]
tx_invpolarity[3:0]
rx_seriallpbken
rx_channelaligned
pll_locked
rx_rmfifoempty[3:0]
rx_rmfifofull[3:0]
rx_disperr[7:0]
rx_errdetect[7:0]
PMA Control and Status Interface Signals–Hard IP Implementation
(Optional)
Signal Name
Table 4–15
signals using the Avalon-MM PHY Management interface to read the control and
status registers which are detailed in
you may need to know the instantaneous value of a signal to ensure correct
functioning of the XAUI PHY. In such cases, you can include the required signal in the
top-level module of your XAUI PHY IP core.
lists the PMA control and status signals. You can access the state of these
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
input
input
input
Dynamically reverse the polarity of every bit of the RX data at the
input of the word aligner.
Force the CDR circuitry to lock to the received data.
When asserted, indicates the RX channel is locked to input data.
Force the receiver CDR to lock to the phase and frequency of the
input reference clock.
When asserted, indicates the RX channel is locked to input
reference clock.
Dynamically reverse the polarity the data word input to the serializer
in the TX datapath.
Serial loopback enable.
■
■
This signal is asynchronous to the receiver. The status of the serial
loopback option is recorded by the PMA channel controller, word
address 0x061.
When asserted indicates that the RX channel is aligned.
In LTR mode, indicates that the receiver CDR has locked to the
phase and frequency of the input reference clock.
Status flag that indicates the rate match FIFO block is empty (5
words). This signal remains high as long as the FIFO is empty and is
asynchronous to the RX datapath.
Status flag that indicates the rate match FIFO block is full (20
words). This signal remains high as long as the FIFO is full and is
asynchronous to the RX data.
Received 10-bit code or data group has a disparity error. It is paired
with rx_errdetect which is also asserted when a disparity error
occurs. The rx_disperr signal is 2 bits wide per channel for a total
of 8 bits per XAUI link.
Transceiver 8B/10B code group violation or disparity error indicator.
If either signal is asserted, a code group violation or disparity error
was detected on the associated received code group. Use the
rx_disperr signal to determine whether this signal indicates a
code group violation or a disparity error. The rx_errdetect signal
is 2 bits wide per channel for a total of 8 bits per XAUI link.
1–enables serial loopback
0–disables serial loopback
Table 4–9 on page
Description
Altera Transceiver PHY IP Core User Guide
4–8. However, in some cases,
4–15